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ADP1046AACPZ-R7 数据表(PDF) 85 Page - Analog Devices |
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ADP1046AACPZ-R7 数据表(HTML) 85 Page - Analog Devices |
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85 / 88 page  Data Sheet ADP1046A Rev. 0 | Page 85 of 88 Table 150. Register 0x45—OUTB Rising Edge Dead Time in Resonant Mode Bits Bit Name R/W Description [7:0] Δt 3 (rising edge dead time of OUTB) R/W This register sets Δt 3, which is the delay time of the rising edge of OUTB from the start of the switching cycle, t A. Each LSB corresponds to 5 ns of resolution. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Δt 3 (ns) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 5 … … … … … … … … … 1 1 1 1 1 1 1 1 1275 Table 151. Register 0x46—Highest Switching Frequency Limit Setting (Minimum Switching Cycle in Resonant Mode) Bits Bit Name R/W Description [7:0] Highest frequency R/W This register contains the eight MSBs of the 12-bit value of the highest switching frequency (mini- mum switching cycle) limit. This value is always used with the top four bits of Register 0x48, which contain the four LSBs of the highest switching frequency limit. Each LSB of the 12-bit value corresponds to 5 ns of resolution for the switching cycle. For example, if Register 0x46 is set to 0x10 (16 decimal) and Bits[7:4] of Register 0x48 are set to 0x9 (9 decimal), the minimum switching cycle is (16 × 16 + 9) × 5 ns = 1.325 μs, and the highest switching frequency limit is 1/1.325 μs = 755 kHz. It is recommended that the maximum frequency be limited to 1 MHz. Table 152. Register 0x47—OUTB Falling Edge Dead Time in Resonant Mode Bits Bit Name R/W Description [7:0] Δt 4 (falling edge dead time of OUTB) R/W This register sets Δt 4, which is the difference between the falling edge of OUTB and the mid- point of the switching cycle, t B. Each LSB corresponds to 5 ns of resolution. When the register value is from 0x00 to 0x7F, the falling edge of OUTB is trailing t B. When the value is from 0x80 to 0xFF, the falling edge of OUTB is leading t B. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Δt 4 0 0 0 0 0 0 0 0 0 ns 0 0 0 0 0 0 0 1 5 ns trailing … … … … … … … … … 0 1 1 1 1 1 1 1 635 ns trailing 1 0 0 0 0 0 0 0 640 ns leading … … … … … … … … … 1 1 1 1 1 1 1 1 5 ns leading Table 153. Register 0x48—Highest Switching Frequency Limit Setting (Minimum Switching Cycle in Resonant Mode) Bits Bit Name R/W Description [7:4] Highest frequency R/W This register contains the four LSBs of the 12-bit value of the highest switching frequency (mini- mum switching cycle) limit. This value is always used with the eight bits of Register 0x46, which contain the eight MSBs of the highest switching frequency limit. Each LSB of the 12-bit value corresponds to 5 ns of resolution for the switching cycle. For example, if Register 0x46 is set to 0x10 (16 decimal) and Bits[7:4] of Register 0x48 are set to 0x9 (9 decimal), the minimum switching cycle is (16 × 16 + 9) × 5 ns = 1.325 μs, and the highest switching frequency limit is 1/1.325 μs = 755 kHz. [3:0] Reserved R/W Reserved. |
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