ADP1046AACPZ-R7 datasheet(54/88 Pages) AD

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ADP1046A

Data Sheet

Rev. 0 | Page 54 of 88

CURRENT SENSE AND CURRENT LIMIT REGISTERS

Table 33. Register 0x21—CS1 Gain Trim

Bits

Bit Name

R/W

Description

Gain polarity

R/W

1 = negative gain is introduced.

0 = positive gain is introduced.

[6:0]

CS1 gain trim

R/W

This value calibrates the primary side current sense gain. See the CS1 Trim section for more

information.

Table 34. Register 0x22—CS1 Accurate OCP Limit

Bits

Bit Name

R/W

Description

[7:5]

CS1 fast OCP blanking

R/W

These bits determine the blanking time for CS1 before fast OCP is enabled. This time is

measured from the start of a switching cycle. If using OUTAUX, the time is synchronized

with the rising edge of OUTAUX.

Bit 7

Bit 6

Bit 5

Delay (ns)

120

200

400

600

800

[4:0]

CS1 accurate OCP

R/W

These bits set the CS1 accurate OCP threshold. The digital word that is output from the CS1 ADC

is compared with this threshold. If the CS1 ADC reading (Register 0x13) is greater than the OCP

threshold set by these bits, the CS1 accurate OCP flag is set. This value should be programmed

only after the CS1 trim has been performed. The range of these bits is from 0 to 31, that is,

0 V to 1.4 V in 43.75 mV steps. The following equation gives the CS1 accurate OCP threshold:

CS1_OCP_Threshold = (CS1_OCP_Limit × 1.4 V/32) + 16 × 1.4/212

Table 35. Register 0x23—CS2 Gain Trim

Bits

Bit Name

R/W

Description

[7:6]

Reserved

R/W

Reserved.

Gain polarity

R/W

1 = negative gain is introduced.

0 = positive gain is introduced.

[4:0]

CS2 gain trim

R/W

This register calibrates the secondary side (CS2) current sense gain. It calibrates for errors in

the sense resistor. See the CS2 Trim section for more information.

Table 36. Register 0x24—CS2 Analog Offset Trim

Bits

Bit Name

R/W

Description

Reserved

R/W

Reserved.

Offset polarity

R/W

1 = negative offset is introduced.

0 = positive offset is introduced.

[5:0]

CS2 offset trim

R/W

This register calibrates the secondary side (CS2) current sense common-mode error. It calibrates

for errors in the resistor divider network. See the CS2 Trim section for more information.

Table 37. Register 0x25—CS2 Digital Offset Trim

Bits

Bit Name

R/W

Description

[7:0]

CS2 digital offset trim

R/W

This register contains the CS2 digital trim level. This value is used to calibrate the CS2 value

that is read in Register 0x18. See the CS2 Trim section for more information.

Table 38. Register 0x26—CS2 Accurate OCP Limit

Bits

Bit Name

R/W

Description

[7:0]

CS2 accurate OCP

R/W

This register sets the CS2 accurate OCP current level. This 8-bit number is compared to the CS2 value

the CS2 accurate OCP flag is set. The following equation gives the CS2 accurate OCP threshold:

CS2_OCP_Threshold = CS2_OCP_Limit × (ADC_Range)/256 + 16 × (ADC_Range)/212

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