ADP1046AACPZ-R7 datasheet(24/88 Pages) AD

24 / 88 page

ADP1046A

Data Sheet

Rev. 0 | Page 24 of 88

VDD

When VDD is applied, a certain time elapses before the part is

capable of regulating the power supply. When VDD rises above

the power-on reset and UVLO levels, it takes approximately

20 μs for VCORE to reach its operational point of 2.5 V. The

EEPROM contents are then downloaded to the registers. The

download takes an additional 25 μs (approximately). After the

EEPROM download, the ADP1046A is ready for operation.

If the ADP1046A is programmed to power up at this time

(PSON is enabled), the soft start ramp begins. Otherwise, the

part waits for the PSON signal.

The proper amount of decoupling capacitance must be placed

between VDD and AGND, as close as possible to the device to

minimize the trace length. It is recommended that the VCORE

pin not be used as a reference or to generate other logic levels

using resistive dividers.

VDD/VCORE OVLO

The ADP1046A has built-in overvoltage protection (OVP) on

its supply rails. When the VDD or VCORE voltage rises above

the OVLO threshold, the response can be programmed using

VCORE OVP fault occurs, the response be set to download the

EEPROM before restarting the part (set Register 0x0E[6] = 1).

POWER GOOD

The ADP1046A has two open-drain power-good pins. The

PGOOD1 pin is driven low when a PGOOD1 fault condition

is present; the PGOOD2 pin is driven low when a PGOOD2

fault condition is present.

The PGOOD1 and PGOOD2 pins and flags can be programmed

to respond to the following flags:

•

Soft start

•

CS1 fast OCP

•

CS1 accurate OCP

•

CS2 accurate OCP

•

UVP

•

Local OVP (fast and accurate)

•

Load OVP

•

OrFET (GATE pin)

The masking of these flags is programmed in Register 0x7B

(for PGOOD1) and Register 0x7C (for PGOOD2). When a flag

is masked, it does not set PGOOD1 or PGOOD2.

The following additional flags can also set the PGOOD2 pin either

unconditionally or based on the flag response, as programmed

in Register 0x2D[3] (see Figure 31 and Table 45).

•

Voltage continuity

•

OrFET disable

•

ACSNS

•

External flag (FLAGIN pin)

•

OTP

These additional flags can be programmed in Register 0x2D[3]

to always set PGOOD2 or to set PGOOD2 only if the flag action

is not set to “ignore” in the fault configuration register for that

flag (see Table 12 and Table 13).

PGOOD1

(FLAG AND PIN)

PGOOD2

(FLAG AND PIN)

ADDITIONAL FLAGS

-VOLTAGE CONTINUITY

-OrFET DISABLE

-ACSNS

-FLAGIN

-OTP

MASKED BY

REG 0x7B

MASKED BY

REG 0x7C

DEBOUNCE

(REG 0x2D[7:6])

DEBOUNCE

(REG 0x2D[5:4])

MAIN FLAGS

-SOFT START

-CS1 FAST OCP

-CS1 ACCURATE OCP

-CS2 ACCURATE OCP

-UVP

-LOCAL OVP

(FAST AND ACCURATE)

-LOAD OVP

-OrFET (GATE PIN)

IF REG 0x2D[3] = 0, THE

ADDITIONAL FLAGS

ALWAYS AFFECT PGOOD2,

REGARDLESS OF THE

PROGRAMMED ACTION.

IF REG 0x2D[3] = 1, THE

ADDITIONAL FLAGS AFFECT

PGOOD2 ONLY IF THEY ARE

NOT SET TO BE IGNORED.

Figure 31. PGOOD1, PGOOD2 Programming

ADP1046AACPZ-R7 数据表(PDF) 24 Page - Analog Devices

ADP1046AACPZ-R7 数据表(HTML) 24 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88

数据表下载