数据搜索系统，热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

预览 PDF HTML

ADP1046AACPZ-R7 数据表(PDF) 69 Page - Analog Devices

部件名 ADP1046AACPZ-R7
功能描述  Digital Controller for Isolated Power Supply Applications
PDF  88 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADP1046AACPZ-R7 数据表(HTML) 69 Page - Analog Devices

Back Button ADP1046AACPZ-R7 Datasheet HTML 65Page - Analog Devices ADP1046AACPZ-R7 Datasheet HTML 66Page - Analog Devices ADP1046AACPZ-R7 Datasheet HTML 67Page - Analog Devices ADP1046AACPZ-R7 Datasheet HTML 68Page - Analog Devices ADP1046AACPZ-R7 Datasheet HTML 69Page - Analog Devices ADP1046AACPZ-R7 Datasheet HTML 70Page - Analog Devices ADP1046AACPZ-R7 Datasheet HTML 71Page - Analog Devices ADP1046AACPZ-R7 Datasheet HTML 72Page - Analog Devices ADP1046AACPZ-R7 Datasheet HTML 73Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 69 / 88 page
background image
Data Sheet
ADP1046A
Rev. 0 | Page 69 of 88
Table 78. Register 0x4E—OUTD Rising Edge Setting (OUTD Pin)
Bits
Bit Name
R/W
Description
[7:4]
t
7
R/W
These bits contain the four LSBs of the 12-bit t
7 time. This value is always used with the eight
bits of Register 0x4D, which contains the eight MSBs of the t
7 time. Each LSB corresponds to
5 ns resolution. The entire switching period is divided into 40 ns time steps. If the t
Rx and tFx of a
PWM edge occur within the same 40 ns time step, the PWM output is 0 V. If the t
Rx and tFx occur
in different 40 ns time steps, the PWM output is set to the programmed value. The absolute
maximum pulse width is t
PERIOD − 5 ns.
3
Modulate enable
R/W
1 = PWM modulation acts on the t
7 edge.
0 = no PWM modulation of the t
7 edge.
2
t
7 sign
R/W
1 = negative sign. Increase of PWM modulation moves t
7 right.
0 = positive sign. Increase of PWM modulation moves t
7 left.
1
Reserved
R/W
Reserved.
0
Volt-second balance
source selection
R/W
If this bit is set to 1, the OUTD rising edge is selected as the start of the integration period for
volt-second balance.
Table 79. Register 0x4F—OUTD Falling Edge Timing (OUTD Pin)
Bits
Bit Name
R/W
Description
[7:0]
t
8
R/W
This register contains the eight MSBs of the 12-bit t
8 time. This value is always used with the top
four bits of Register 0x50, which contains the four LSBs of the t
8 time. Each LSB corresponds to
5 ns resolution. The entire switching period is divided into 40 ns time steps. If the t
Rx and tFx of a
PWM edge occur within the same 40 ns time step, the PWM output is 0 V. If the t
Rx and tFx occur
in different 40 ns time steps, the PWM output is set to the programmed value. The absolute
maximum pulse width is t
PERIOD − 5 ns.
Table 80. Register 0x50—OUTD Falling Edge Setting (OUTD Pin)
Bits
Bit Name
R/W
Description
[7:4]
t
8
R/W
These bits contain the four LSBs of the 12-bit t
8 time. This value is always used with the eight
bits of Register 0x4F, which contains the eight MSBs of the t
8 time. Each LSB corresponds to
5 ns resolution. The entire switching period is divided into 40 ns time steps. If the t
Rx and tFx of a
PWM edge occur within the same 40 ns time step, the PWM output is 0 V. If the t
Rx and tFx occur
in different 40 ns time steps, the PWM output is set to the programmed value. The absolute
maximum pulse width is t
PERIOD − 5 ns.
3
Modulate enable
R/W
1 = PWM modulation acts on the t
8 edge.
0 = no PWM modulation of the t
8 edge.
2
t
8 sign
R/W
1 = negative sign. Increase of PWM modulation moves t
8 right.
0 = positive sign. Increase of PWM modulation moves t
8 left.
[1:0]
Reserved
R/W
Reserved.
Table 81. Register 0x51—SR1 Rising Edge Timing (SR1 Pin)
Bits
Bit Name
R/W
Description
[7:0]
t
9
R/W
This register contains the eight MSBs of the 12-bit t
9 time. This value is always used with the top
four bits of Register 0x52, which contains the four LSBs of the t
9 time. Each LSB corresponds to
5 ns resolution. The entire switching period is divided into 40 ns time steps. If the t
Rx and tFx of a
PWM edge occur within the same 40 ns time step, the PWM output is 0 V. If the t
Rx and tFx occur
in different 40 ns time steps, the PWM output is set to the programmed value. The absolute
maximum pulse width is t
PERIOD − 5 ns. It is recommended that the SR1 rising edge not be set
between 80 ns and 115 ns when using the SR soft start.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com