PCMB065T-R68MS datasheet(18/46 Pages) IRF

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JANURARY 18, 2013 | DATA SHEET | Rev 3.5

IR3898

6A Highly Integrated SupIRBuck

Single-Input Voltage, Synchronous Buck Regulator

PD-97662

THEORY OF OPERATION

DESCRIPTION

The IR3898 uses a PWM voltage mode control scheme with

external compensation to provide good noise immunity

and maximum flexibility in selecting inductor values and

capacitor types.

The switching frequency is programmable from 300kHz

to 1.5MHz and provides the capability of optimizing the

design in terms of size and performance.

IR3898 provides precisely regulated output voltage

programmed via two external resistors from 0.5V to

0.86*Vin.

The IR3898 operates with an internal bias supply (LDO)

which is connected to the Vcc/LDO_out pin. This allows

operation with single supply. The bias voltage is variable

according to load condition. If the output load current is

less than half of the peak-to-peak inductor current, a lower

bias voltage, 4.4V, is used as the internal gate drive

voltage; otherwise, a higher voltage, 6.4V, is used.

This feature helps the converter to reduce power losses.

The device can also be operated with an external supply

from 4.5 to 7.5V, allowing an extended operating input

voltage (PVin) range from 1.0V to 16V. For using the

internal LDO supply, the Vin pin should be connected to

PVin pin. If an external supply is used, it should be

connected to Vcc/LDO_Out pin and the Vin pin should be

shorted to Vcc/LDO_Out pin.

The device utilizes the on-resistance of the low side

MOSFET (sync FET) for over current protection. This

method enhances the converter’s efficiency and reduces

cost by eliminating the need for external current sense

resistor.

IR3898 includes two low Rds(on) MOSFETs using IR’s HEXFET

technology. These are specifically designed for high

efficiency applications.

UNDER-VOLTAGE LOCKOUT AND POR

The under-voltage lockout circuit monitors the voltage of

Vcc/LDO_Out pin and the Enable input. It assures that the

MOSFET driver outputs remain in the off state whenever

either of these two signals drop below the set thresholds.

Normal operation resumes once Vcc/LDO_Out and Enable

rise above their thresholds.

The POR (Power On Ready) signal is generated when all

these signals reach the valid logic level (see system block

diagram). When the POR is asserted the soft start

sequence starts (see soft start section).

ENABLE

The Enable features another level of flexibility for start up.

The Enable has precise threshold which is internally

monitored by Under-Voltage Lockout (UVLO) circuit.

Therefore, the IR3898 will turn on only when the voltage

at the Enable pin exceeds this threshold, typically, 1.2V.

If the input to the Enable pin is derived from the bus

voltage by a suitably programmed resistive divider, it can

be ensured that the IR3898 does not turn on until the bus

voltage reaches the desired level (Fig. 4). Only after the bus

voltage reaches or exceeds this level and voltage at the

Enable pin exceeds its threshold, IR3898 will be enabled.

Therefore, in addition to being a logic input pin to enable

the IR3898, the Enable feature, with its precise threshold,

also allows the user to implement an Under-Voltage

Lockout for the bus voltage (PVin). This is desirable

particularly for high output voltage applications, where we

might want the IR3898 to be disabled at least until PVIN

exceeds the desired output voltage level.

Pvin (12V)

Vcc

Enable

Intl_SS

10. 2 V

Enable Threshold = 1.2V

Figure 4: Normal Start up, device turns on

when the bus voltage reaches 10.2V

A resistor divider is used at EN pin from PVin to turn on the

device at 10.2V.

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