PCMB065T-R68MS datasheet(19/46 Pages) IRF

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JANURARY 18, 2013 | DATA SHEET | Rev 3.5

IR3898

6A Highly Integrated SupIRBuck

Single-Input Voltage, Synchronous Buck Regulator

PD-97662

Pvin(12V)

Vcc

Intl_SS

Enable >1.2V

Vp>1V

Figure 5a: Recommended startup for Normal operation

Pvin (12V)

Vcc

Enable> 1. 2 V

Intl_SS

Figure 5b: Recommended startup for sequencing operation

(ratiometric or simultaneous)

Pvin=Vin=12V

Vp=VDDQ/2

Vcc

Vref=0

Enable > 1.2V

VTT

VDDQ

VTT Tracking

Figure 5c: Recommended startup for

memory tracking operation (VTT-DDR4)

Figure 5a shows the recommended start-up sequence for

the normal (non-tracking, non-sequencing) operation of

IR3898, when Enable is used as logic input. Figure 5b

shows the recommended startup sequence for sequenced

operation of IR3898 with Enable used as logic input. Figure

5c shows the recommended startup sequence for tracking

operation of IR3898 with Enable used as logic input.

In normal and sequencing mode operation, Vref is left

floating. A 100pF ceramic capacitor is recommended

between this pin and Gnd. In tracking mode operation,

Vref should be tied to Gnd.

It is recommended to apply the Enable signal after the VCC

voltage has been established. If the Enable signal is present

before VCC, a 50kΩ resistor can be used in series with the

Enable pin to limit the current flowing into the Enable pin.

PRE-BIAS STARTUP

IR3898 is able to start up into pre-charged output, which

prevents oscillation and disturbances of the output

voltage.

The output starts in asynchronous fashion and keeps the

synchronous MOSFET (Sync FET) off until the first gate

signal for control MOSFET (Ctrl FET) is generated. Figure 6a

shows a typical Pre-Bias condition at start up. The sync FET

always starts with a narrow pulse width (12.5% of a

switching period) and gradually increases its duty cycle

with a step of 12.5% until it reaches the steady state value.

The number of these startup pulses for each step is 16 and

it’s internally programmed. Figure 6b shows the series of

16x8 startup pulses.

[V]

[Time]

Pre-Bias

Voltage

Figure 6a: Pre-Bias startup

...

HDRv

...

End of

LDRv

12.5%

25%

87.5%

...

Figure 6b: Pre-Bias startup pulses

PCMB065T-R68MS 数据表(PDF) 19 Page - International Rectifier

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