MPC8358ECVVADDGA datasheet(37/102 Pages) FREESCALE

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MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5

Freescale Semiconductor

Ethernet Management Interface Electrical Characteristics

8.3.2

MII Management AC Electrical Specifications

This table provides the MII management AC timing specifications.

This figure shows the MII management AC timing diagram.

Figure 21. MII Management Interface Timing Diagram

Table 37. MII Management AC Timing Specifications

At recommended operating conditions with LVDD is 3.3 V ± 10%.

Parameter/Condition

Symbol1

Min

Typ

Max

Unit

Notes

MDC frequency

fMDC

—2.5

—

MHz

MDC period

tMDC

—400

—

MDC clock pulse width high

tMDCH

—

MDC to MDIO delay

tMDTKHDX

tMDTKHDV

—

——

110

MDIO to MDC setup time

tMDRDVKH

—

MDIO to MDC hold time

tMDRDXKH

0—

—

MDC rise time

tMDCR

—

MDC fall time

tMDHF

—

Notes:

1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX symbolizes

management data timing (MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are invalid (X) or

data hold time. Also, tMDRDVKH symbolizes management data timing (MD) with respect to the time data input signals (D)

reach the valid state (V) relative to the tMDC clock reference (K) going to the high (H) state or setup time. For rise and fall

times, the latter convention is used with the appropriate letter: R (rise) or F (fall).

2. This parameter is dependent on the csb_clk speed (that is, for a csb_clk of 267 MHz, the maximum frequency is 8.3 MHz

and the minimum frequency is 1.2 MHz; for a csb_clk of 375 MHz, the maximum frequency is 11.7 MHz and the minimum

frequency is 1.7 MHz).

3. This parameter is dependent on the ce_clk speed (that is, for a ce_clk of 200 MHz, the delay is 90 ns and for a ce_clk of

300 MHz, the delay is 63 ns).

MDC

tMDRDXKH

tMDC

tMDCH

tMDCR

tMDHF

tMDTKHDX

MDIO

(Input)

(Output)

tMDRDVKH

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