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MPC8358ECVVADDGA 数据表(PDF) 10 Page - Freescale Semiconductor, Inc |
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MPC8358ECVVADDGA 数据表(HTML) 10 Page - Freescale Semiconductor, Inc |
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10 / 102 page ![]() MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5 10 Freescale Semiconductor Overall DC Electrical Characteristics This figure shows the undershoot and overshoot voltages at the interfaces of the device. Figure 3. Overshoot/Undershoot Voltage for GVDD/OVDD/LVDD PCI, local bus, DUART, system control and power management, I2C, SPI, and JTAG I/O voltage OVDD 3.3 V ± 330 mV V — Junction temperature TJ 0 to 105 –40 to 105 ° C 2 Notes: 1. GVDD, LVDD, OVDD, AVDD, and VDD must track each other and must vary in the same direction—either in the positive or negative direction. 2. The operating conditions for junction temperature, TJ, on the 600/333/400 MHz and 500/333/500 MHz on rev. 2.0 silicon is 0 ° to 70 ° C. Refer to Errata General9 in Chip Errata for the MPC8360E, Rev. 1. 3. For more information on Part Numbering, refer to Table 80. Table 2. Recommended Operating Conditions (continued) Characteristic Symbol Recommended Value Unit Notes GND GND – 0.3 V GND – 0.7 V Not to Exceed 10% G/L/OVDD + 20% G/L/OVDD G/L/OVDD + 5% of tinterface 1 1. Note that tinterface refers to the clock period associated with the bus clock interface. VIH VIL Note: |
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