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MPC8358ECVVADDGA 数据表(PDF) 7 Page - Freescale Semiconductor, Inc

部件名 MPC8358ECVVADDGA
功能描述  PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications
PDF  102 Pages
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制造商  FREESCALE [Freescale Semiconductor, Inc]
网页  http://www.freescale.com
标志 FREESCALE - Freescale Semiconductor, Inc

MPC8358ECVVADDGA 数据表(HTML) 7 Page - Freescale Semiconductor, Inc

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MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
Freescale Semiconductor
7
— Programmable highest priority request
— Four groups of interrupts with programmable priority
— External and internal interrupts directed to communication processor
— Redirects interrupts to external INTA pin when in core disable mode
— Unique vector number for each interrupt source
Dual industry-standard I2C interfaces
— Two-wire interface
— Multiple master support
— Master or slave I2C mode support
— On-chip digital filtering rejects spikes on the bus
— System initialization data is optionally loaded from I2C-1 EPROM by boot sequencer embedded hardware
DMA controller
— Four independent virtual channels
— Concurrent execution across multiple channels with programmable bandwidth control
— All channels accessible by local core and remote PCI masters
— Misaligned transfer capability
— Data chaining and direct mode
— Interrupt on completed segment and chain
— DMA external handshake signals: DMA_DREQ[0:3]/DMA_DACK[0:3]/DMA_DONE[0:3]. There is one set for
each DMA channel. The pins are multiplexed to the parallel IO pins with other QE functions.
•DUART
— Two 4-wire interfaces (RxD, TxD, RTS, CTS)
— Programming model compatible with the original 16450 UART and the PC16550D
System timers
— Periodic interrupt timer
— Real-time clock
— Software watchdog timer
— Eight general-purpose timers
IEEE Std. 1149.1™-compliant, JTAG boundary scan
Integrated PCI bus and SDRAM clock generation
2
Electrical Characteristics
This section provides the AC and DC electrical specifications and thermal characteristics for the MPC8360E/58E. The device
is currently targeted to these specifications. Some of these specifications are independent of the I/O cell, but are included for a
more complete reference. These are not purely I/O buffer design specifications.



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