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MPC8358ECVVADDGA 数据表(PDF) 39 Page - Freescale Semiconductor, Inc |
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MPC8358ECVVADDGA 数据表(HTML) 39 Page - Freescale Semiconductor, Inc |
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39 / 102 page  MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5 Freescale Semiconductor 39 Local Bus AC Electrical Specifications This table describes the general timing parameters of the local bus interface of the device. LUPWAIT input hold from local bus clock tLBIXKH2 1.0 — ns 3, 4 LALE output fall to LAD output transition (LATCH hold time) tLBOTOT1 1.5 — ns 5 LALE output fall to LAD output transition (LATCH hold time) tLBOTOT2 3.0 — ns 6 LALE output fall to LAD output transition (LATCH hold time) tLBOTOT3 2.5 — ns 7 Local bus clock to LALE rise tLBKHLR —4.5 ns — Local bus clock to output valid (except LAD/LDP and LALE) tLBKHOV1 —4.5 ns — Local bus clock to data valid for LAD/LDP tLBKHOV2 —4.5 ns 3 Local bus clock to address valid for LAD tLBKHOV3 —4.5 ns 3 Output hold from local bus clock (except LAD/LDP and LALE) tLBKHOX1 1.0 — ns 3 Output hold from local bus clock for LAD/LDP tLBKHOX2 1.0 — ns 3 Local bus clock to output high impedance for LAD/LDP tLBKHOZ —3.8 ns 8 Notes: 1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1 symbolizes local bus timing (LB) for the input (I) to go invalid (X) with respect to the time the tLBK clock reference (K) goes high (H), in this case for clock one (1). Also, tLBKHOX symbolizes local bus timing (LB) for the tLBK clock reference (K) to go high (H), with respect to the output (O) going invalid (X) or output hold time. 2. All timings are in reference to rising edge of LSYNC_IN. 3. All signals are measured from OVDD/2 of the rising edge of LSYNC_IN to 0.4 × OVDD of the signal in question for 3.3-V signaling levels. 4. Input timings are measured at the pin. 5. tLBOTOT1 should be used when RCWH[LALE] is not set and when the load on LALE output pin is at least 10 pF less than the load on LAD output pins. 6. tLBOTOT2 should be used when RCWH[LALE] is set and when the load on LALE output pin is at least 10 pF less than the load on LAD output pins. 7. tLBOTOT3 should be used when RCWH[LALE] is set and when the load on LALE output pin equals to the load on LAD output pins. 8. For purposes of active/float timing measurements, the Hi-Z or off-state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. Table 41. Local Bus General Timing Parameters—DLL Bypass Mode9 Parameter Symbol1 Min Max Unit Notes Local bus cycle time tLBK 15 — ns 2 Input setup to local bus clock tLBIVKH 7— ns 3, 4 Input hold from local bus clock tLBIXKH 1.0 — ns 3, 4 LALE output fall to LAD output transition (LATCH hold time) tLBOTOT1 1.5 — ns 5 LALE output fall to LAD output transition (LATCH hold time) tLBOTOT2 3— ns 6 LALE output fall to LAD output transition (LATCH hold time) tLBOTOT3 2.5 — ns 7 Table 40. Local Bus General Timing Parameters—DLL Enabled (continued) Parameter Symbol1 Min Max Unit Notes |
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