AM79C970A datasheet(32/219 Pages) AMD

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P R E L I M I N A R Y

Am79C970A

19436A-5

FRAME

CLK

IRDY

TRDY

DEVSEL

STOP

IDSEL

23456

1011

PAR

DATA

ADDR

Figure 2. Slave Configuration Write

Slave I/O Transfers

After the PCnet-PCI II controller is configured as an I/O

device by setting IOEN (for regular I/O mode) or

MEMEN (for memory mapped I/O mode) in the PCI

Command register, it starts monitoring the PCI bus for

access to its CSR, BCR or EEPROM locations. If config-

ured for regular I/O mode, the PCnet-PCI II controller

will look for an address that falls within its 32 bytes of I/O

address space (starting from the I/O base address). The

PCnet-PCI II controller asserts

DEVSEL if it detects an

address match and the access is an I/O cycle. If config-

ured for memory mapped I/O mode, the PCnet-PCI II

controller will look for an address that falls within its 32

bytes of memory address space (starting from the mem-

ory mapped I/O base address). The PCnet-PCI II con-

troller asserts

DEVSEL if it detects an address match

and the access is a memory cycle.

DEVSEL is asserted

two clock cycles after the host has asserted

FRAME.

The PCnet-PCI II controller will not assert

DEVSEL if it

detects an address match, but the PCI command is not

of the correct type. In memory mapped I/O mode, the

PCnet-PCI II controller aliases all accesses to the I/O re-

sources of the command types “Memory Read Multiple”

and “Memory Read Line” to the basic Memory Read

command. All accesses of the type “Memory Write and

Invalidate” are aliased to the basic Memory Write com-

mand. 8-bit, 16-bit and 32-bit non-burst transactions are

supported. The PCnet-PCI II controller decodes only the

upper 30 address lines to determine which I/O resource

is accessed.

The typical number of wait states added to a slave I/O or

memory mapped I/O read or write access on the part of

the PCnet-PCI II controller is 6 to 7 clock cycles,

depending upon the relative phases of the internal

Buffer Management Unit clock and the CLK signal,

since the internal Buffer Management Unit clock is a

divide-by-two version of the CLK signal.

The PCnet-PCI II controller does not support burst

transfers for access to its I/O resources. When the host

keeps

FRAME asserted for a second data phase,

the PCnet-PCI II controller will disconnect the transfer.

The PCnet-PCI II controller supports fast back-to-back

transactions to different targets. This is indicated by the

Fast Back-To-Back Capable bit (PCI Status register,

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