AM79C970A datasheet(63/219 Pages) AMD

63 / 219 page

P R E L I M I N A R Y

AMD

Am79C970A

threshold (write transfers), or until the DMA Bus Activity

Timer (CSR82) has expired. The exact number of total

transfer cycles in the bus mastership period is depend-

ent on all of the following variables: the settings of the

FIFO watermarks, the conditions of the FIFOs, the

latency of the system bus to the PCnet-PCI II controller’s

bus request, the speed of bus operation and bus

preemption events. The DMA Transfer Counter is

disabled when DMAPLUS is set to ONE. The

TRDY re-

sponse time of the memory device will also affect the

number of transfers, since the speed of the accesses

will affect the state of the FIFO. During accesses, the

FIFO may be filling or emptying on the network end. For

example, on a receive operation, a slower

TRDY re-

sponse will allow additional data to accumulate inside of

the FIFO. If the accesses are slow enough, a complete

DWord may become available before the end of the bus

mastership period and thereby increase the number of

transfers in that period. The general rule is that the

longer the Bus Grant latency, the slower the bus transfer

operations, the slower the clock speed, the higher the

transmit watermark or the lower the receive watermark,

the longer the bus mastership period will be.

Note that the PCI Latency Timer is not significant during

non-burst transfers.

Burst FIFO DMA Transfers

Bursting is only performed by the PCnet-PCI II controller

if the BREADE and/or BWRITE bits of BCR18 are set.

These bits individually enable/disable the ability of the

PCnet-PCI II controller to perform burst accesses

during master read operations and master write

operations, respectively.

A burst transaction will start with an address phase, fol-

lowed by one or more data phases. AD[1:0] will always

be ZERO during the address phase indicating a linear

burst order.

During FIFO DMA read operations, all byte lanes will al-

ways be active. The PCnet-PCI II controller will inter-

nally discard unused bytes. During the first and the last

data phases of a FIFO DMA burst write operation, one or

more of the byte enable signals may be inactive. All

other data phases will always write a complete DWord.

AM79C970A 数据表(PDF) 63 Page - Advanced Micro Devices

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