AM79C970A datasheet(76/219 Pages) AMD

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AMD

P R E L I M I N A R Y

Am79C970A

Preamble

1010....1010

SFD

10101011

Destination

Address

Source

Address

Length

LLC

Data

Pad

FCS

Bytes

46 – 1500

Bytes

Bits

19436A-37

Figure 34. ISO 8802-3 (IEEE/ANSI 802.3) Data Frame

The 544 bit count is derived from the following :

Minimum frame size (excluding

64 bytes 512 bits

preamble/SFD, including FCS)

Preamble/SFD size

8 bytes

64 bits

FCS size

4 bytes

32 bits

At the point that FCS is to be appended, the transmit-

ted frame should contain:

Preamble/SFD + (Min Frame Size – FCS)

64 + (512 – 32) = 544 bits

A minimum length transmit frame from the PCnet-PCI II

controller will therefore be 576 bits, after the FCS

is appended.

Transmit FCS Generation

Automatic generation and transmission of FCS for a

transmit frame depends on the value of DXMTFCS

(CSR15, bit 3). If DXMTFCS is cleared to ZERO, the

transmitter will generate and append the FCS to the

transmitted frame. If the automatic padding feature is in-

voked (APAD_XMT is set in CSR4), the FCS will be ap-

pended by the PCnet-PCI II controller regardless of the

state of DXMTFCS or ADD_FCS/NO_FCS (TMD1, bit

29). Note that the calculated FCS is transmitted most

significant bit first. The default value of DXMTFCS is 0

after H_RESET.

ADD_FCS (TMD1, bit 29) allows the automatic genera-

tion and transmission of FCS on a frame by frame basis.

DXMTFCS should be cleared to ZERO in this mode. To

generate FCS for a frame, ADD_FCS must be set in the

first descriptor of a frame (STP is set to ONE). Note that

bit 29 of TMD1 has the function of ADD_FCS if

SWSTYLE (BCR20, bits 7–0) is programmed to ZERO,

TWO or THREE.

When SWSTYLE is set to ONE for ILACC backwards

compatibility, bit 29 of TMD1 changes its function to

NO_FCS. When DXMTFCS is cleared to ZERO and

NO_FCS is set to ONE in the last descriptor of a frame

(ENP is set to ONE), the PCnet-PCI II controller will not

generate and append an FCS to a transmit frame.

Transmit Exception Conditions

Exception conditions for frame transmission fall into two

distinct categories. Those which are the result of normal

network operation, and those which occur due to abnor-

mal network and/or host related events.

Normal events which may occur and which are handled

autonomously by the PCnet-PCI II controller include col-

lisions within the slot time with automatic retry. The

PCnet-PCI II controller will ensure that collisions which

occur within 512 bit times from the start of transmission

(including preamble) will be automatically retried with no

host intervention. The transmit FIFO ensures this by

guaranteeing that data contained within the FIFO will

not be overwritten until at least 64 bytes (512 bits) of pre-

amble plus address, length and data fields have been

transmitted onto the network without encountering a col-

lision. Note that if DRTY (CSR15, bit 5) is set to ONE or if

the network interface is operating in full-duplex mode,

no collision handling is required, and any byte of frame

data in the FIFO can be overwritten as soon as it

is transmitted.

If 16 total attempts (initial attempt plus 15 retries) fail, the

PCnet-PCI II controller sets the RTRY bit in the current

transmit TDTE in host memory (TMD2), gives up

ownership (resets the OWN bit to ZERO) for this frame,

and processes the next frame in the transmit ring

for transmission.

Abnormal network conditions include:

s Loss of carrier.

s Late collision.

s SQE Test Error. (Does not apply to 10BASE-T port.)

These conditions should not occur on a correctly config-

ured 802.3 network operating in half-duplex mode, and

will be reported if they do. None of these conditions will

occur on a network operating in full-duplex mode. (See

the section “Full-Duplex Operation” for more detail.)

When an error occurs in the middle of a multi-buffer

frame transmission, the error status will be written in the

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