AM79C970A datasheet(43/219 Pages) AMD

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P R E L I M I N A R Y

AMD

Am79C970A

19436A-15

FRAME

CLK

IRDY

REQ

GNT

2345

CMD

ADDR

Figure 12. Bus Acquisition

Bus Master DMA Transfers

There are four primary types of DMA transfers. The

PCnet-PCI II controller uses non-burst as well as burst

cycles for read and write access to the main memory.

Basic Non-Burst Read Transfer

By default, the PCnet-PCI II controller uses non-burst

cycles

all

bus

master

read

operations.

All

PCnet-PCI II controller non-burst read accesses are of

the PCI command type Memory Read (type 6). Note that

during a non-burst read operation, all byte lanes will al-

ways be active. The PCnet-PCI II controller will inter-

nally discard unneeded bytes.

The PCnet-PCI II controller typically performs more

than one non-burst read transactions within a single bus

mastership period.

FRAME is dropped between con-

secutive non-burst read cycles.

REQ however stays

asserted until

FRAME is asserted for the last

transaction. The PCnet-PCI II controller supports zero

wait state read cycles. It asserts

IRDY immediately after

the address phase and at the same time starts

sampling

DEVSEL.

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