AM79C970A datasheet(84/219 Pages) AMD

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Am79C970A

interrupts the receive oscillator. The oscillator is then re-

started at the second Manchester ZERO (bit time 4) and

is phase locked to it. As a result, the MENDEC acquires

the clock from the incoming Manchester bit pattern in 4

bit times with a 1010b Manchester bit pattern.

IRXCLK and IRXDAT are enabled 1/4 bit time after clock

acquisition in bit cell 5. IRXDAT is at a HIGH state when

the receiver is idle (no IRXCLK). IRXDAT however, is

undefined when clock is acquired and may remain HIGH

or change to LOW state whenever IRXCLK is enabled.

At 1/4 bit time into bit cell 5, the controller portion of the

PCnet-PCI II controller sees the first IRXCLK transition.

This also strobes in the incoming fifth bit to the MENDEC

as Manchester ONE. IRXDAT may make a transition af-

ter the IRXCLK rising edge in bit cell 5, but its state is still

undefined. The Manchester ONE at bit 5 is clocked to

IRXDAT output at 1/4 bit time in bit cell 6.

PLL Tracking

After clock acquisition, the phase-locked clock is com-

pared to the incoming transition at the bit cell center

(BCC) and the resulting phase error is applied to a cor-

rection circuit. This circuit ensures that the phase-

locked clock remains locked on the received signal.

Individual bit cell phase corrections of the Voltage Con-

trolled Oscillator (VCO) are limited to 10% of the phase

difference between BCC and phase-locked clock.

Hence, input data jitter is reduced in IRXCLK by 10 to 1.

Carrier Tracking and End of Message

The carrier detection circuit monitors the DI

± inputs after

IRXEN is asserted for an end of message. IRXEN deas-

serts 1 to 2 bit times after the last positive transition on

the incoming message. This initiates the end of recep-

tion cycle. The time delay from the last rising edge of the

message to IRXEN deassert allows the last bit to be

strobed by IRXCLK and transferred to the controller sec-

tion, but prevents any extra bit(s) at the end of message.

Data Decoding

The data receiver is a comparator with clocked output to

minimize noise sensitivity to the DI

± inputs. Input error is

less than

± 35 mV to minimize sensitivity to input rise

and fall time. IRXCLK strobes the data receiver output at

1/4 bit time to determine the value of the Manchester bit,

and clocks the data out on IRXDAT on the following

IRXCLK. The data receiver also generates the signal

used for phase detector comparison to the internal

MENDEC voltage controlled oscillator (VCO).

Jitter Tolerance Definition

The MENDEC utilizes a clock capture circuit to align its

internal data strobe with an incoming bit stream. The

clock acquisition circuitry requires four valid bits with the

values 1010b. The clock is phase-locked to the negative

transition at the bit cell center of the second ZERO in

the pattern.

Since data is strobed at 1/4 bit time, Manchester transi-

tions which shift from their nominal placement through

1/4 bit time will result in improperly decoded data. With

this as the criterion for an error, a definition of Jitter

Handling is:

The peak deviation approaching or crossing 1/4 bit cell

position from nominal input transition, for which the

MENDEC section will properly decode data.

Attachment Unit Interface

The Attachment Unit Interface (AUI) is the PLS (Physi-

cal Layer Signaling) to PMA (Physical Medium Attach-

ment) interface which effectively connects the DTE to a

MAU. The differential interface provided by the

PCnet-PCI II controller is fully compliant to Section 7 of

ISO 8802-3 (ANSI/IEEE 802.3).

After the PCnet-PCI II controller initiates a transmission

it will expect to see data “looped-back” on the DI

± pair

(when the AUI port is selected). This will internally gen-

erate a “carrier sense”, indicating that the integrity of the

data path to and from the MAU is intact, and that the

MAU is operating correctly. This “carrier sense” signal

must be asserted before end of transmission. If ”carrier

sense” does not become active in response to the data

transmission, or becomes inactive before the end of

transmission, the loss of carrier (LCAR) error bit will be

set in the transmit descriptor ring (TMD2, bit 27) after the

frame has been transmitted.

Differential Input Termination

The differential input for the Manchester data (DI

±) is

externally terminated by two 40.2

Ω resistors and one

optional common-mode bypass capacitor, as shown in

the diagram below. The differential input impedance,

ZIDF, and the common-mode input impedance, ZICM,

are specified so that the Ethernet specification for cable

termination impedance is met using standard 1% resis-

tor terminators. If SIP devices are used, 39 ohms is also

a suitable value. The CI

± differential inputs are termi-

nated in exactly the same way as the DI

± pair.

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