AM79C970A datasheet(97/219 Pages) AMD

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P R E L I M I N A R Y

AMD

Am79C970A

Power Savings Modes

The PCnet-PCI II controller supports two hardware

power savings modes. Both are entered by driving the

SLEEP pin LOW.

The power down mode that yields the most power sav-

ings is called coma mode. In coma mode, the entire

device is shut down. All inputs are ignored except the

SLEEP pin itself. Coma mode is enabled when AWAKE

(BCR2, bit 2) is at its default value of ZERO and

SLEEP

is asserted.

The second power saving mode is called snooze mode.

In snooze mode, enabled by setting AWAKE to ONE

and driving the

SLEEP pin LOW, the T-MAU receive cir-

cuitry will remain active even while the

SLEEP pin is

driven LOW. The

LNKST output is the only one of the

LED pins that continues to function. All other sections of

the device are shut down. The LNKSTE bit must be set

in BCR4 to enable indication of a good 10BASE-T link if

there are link beat pulses or valid frames present. This

LNKST pin can be used to drive an LED and/or external

hardware that directly controls the

SLEEP pin of the

PCnet-PCI II controller. This configuration effectively

wakes the system when there is any activity on the

10BASE-T link. Snooze mode can be used only if the

T-MAU is the selected network port. Link beat pulses

are not transmitted during snooze mode.

The

SLEEP pin must not be asserted while the PCnet-

PCI II controller is requesting the bus or while a slave or

bus master cycle is in progress. A recommended

method is to set the PCnet-PCI II controller into

suspend mode by setting the SPND bit in CSR5 to ONE

prior to asserting the

SLEEP pin. Another recom-

mended method is to

stop the device by setting the

STOP bit in CSR0 to ONE prior to asserting the

SLEEP pin.

Before the sleep mode is invoked, the PCnet-PCI II

controller will perform an internal S_RESET. This

S_RESET operation will not affect the values of the BCR

registers or the PCI configuration space. S_RESET ter-

minates all network activity abruptly. The host can use

the suspend mode (SPND, CSR5, bit 0) to terminate all

network activity in an orderly sequence before issuing

an S_RESET.

When coming out of the sleep mode, the PCnet-PCI II

controller can be programmed to generate an interrupt

and inform the driver about the wake-up. The

PCnet-PCI II controller will set SLPINT (CSR5, bit 9),

when coming out of the sleep mode.

INTA will be

asserted, when the enable bit SLPINTE (CSR5, bit 8) is

set to ONE. Note that the assertion of

INTA due to

SLPINT is not dependent on the main interrupt enable

bit INEA (CSR0, bit 6), which will be cleared by the reset

going into the sleep mode.

The

SLEEP pin should not be asserted during power

supply ramp-up. If it is desired that

SLEEP be asserted

at power up time, then the system must delay the asser-

tion of

SLEEP until three clock cycles after the comple-

tion of a hardware reset operation.

IEEE 1149.1 Test Access Port Interface

An IEEE 1149.1 compatible boundary scan Test Access

Port is provided for board level continuity test and diag-

nostics. All digital input, output and input/output pins are

tested. Analog pins, including the AUI differential driver

(DO

±) and receivers (DI±, CI±), and the crystal input

(XTAL1/XTAL2) pins, are not tested. The T-MAU drivers

TXD

±, TXP± and receiver RXD± are also not tested.

The following is a brief summary of the IEEE 1149.1

compatible

test

functions

implemented

the

PCnet-PCI II controller.

Boundary Scan Circuit

The boundary scan test circuit requires four pins (TCK,

TMS, TDI and TDO), defined as the Test Access Port

(TAP). It includes a finite state machine (FSM), an in-

struction register, a data register array, and a power-on

reset circuit. Internal pull-up resistors are provided for

the TDI, TCK, and TMS pins. The boundary scan circuit

remains active during Sleep mode.

TAP Finite State Machine

The TAP engine is a 16-state finite state machine

(FSM), driven by the Test Clock (TCK) and the Test

Mode Select (TMS) pins. An independent power-on

reset circuit is provided to ensure the FSM is in the

TEST_LOGIC_RESET state at power-up. The FSM

is also reset when TMS and TDI are high for five

TCK periods.

Supported Instructions

In addition to the minimum IEEE 1149.1 requirements

(BYPASS, EXTEST, and SAMPLE instructions), three

additional

instructions

(IDCODE,

TRIBYP

and

SETBYP) are provided to further ease board-level test-

ing. All unused instruction codes are reserved. See the

following table for a summary of supported instructions.

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