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AM79C970A 数据表(PDF) 47 Page - Advanced Micro Devices |
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AM79C970A 数据表(HTML) 47 Page - Advanced Micro Devices |
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47 / 219 page  P R E L I M I N A R Y AMD 47 Am79C970A The following figure shows a typical burst write access. The PCnet-PCI II controller arbitrates for the bus, is granted access, and writes four 32-bit words (DWords) to the system memory and then releases the bus. In this example, the memory system extends the data phase of the first access by one wait state. The following three data phases take one clock cycle each, which is deter- mined by the timing of TRDY. The example assumes that EXTREQ (BCR18, bit 8) is set to ONE, therefore, REQ is not deasserted until the next to last data phase is finished. 19436A-19 FRAME CLK AD IRDY TRDY C/ BE DEVSEL REQ GNT 1 2345678 ADDR DATA DATA DATA BE 0111 9 PAR PAR PAR PAR PAR DATA PAR DEVSEL is sampled Figure 16. Burst Write Transfer (EXTREQ = 1) |
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