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AM79C970A 数据表(PDF) 48 Page - Advanced Micro Devices |
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AM79C970A 数据表(HTML) 48 Page - Advanced Micro Devices |
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48 / 219 page ![]() AMD P R E L I M I N A R Y 48 Am79C970A Target Initiated Termination When the PCnet-PCI II controller is a bus master, the cycles it produces on the PCI bus may be terminated by the target in one of three different ways. Disconnect With Data Transfer The figure below shows a disconnection in which one last data transfer occurs after the target asserted STOP. STOP is asserted on clock 4 to start the termination sequence. Data is still transferred during this cycle, since both IRDY and TRDY are asserted. The PCnet-PCI II controller terminates the current transfer with the deassertion of FRAME on clock 5 and of IRDY one clock later. It finally releases the bus on clock 6. The PCnet-PCI II controller will re-request the bus after 2 clock cycles, if it wants to transfer more data. The start- ing address of the new transfer will be the address of the next untransferred data. 19436A-20 FRAME CLK AD IRDY TRDY C/ BE DEVSEL REQ GNT PAR DEVSEL is sampled ADDRi 0000 0111 PAR 0111 1 2345678 10 9 PAR DATA STOP ADDRi+8 DATA Figure 17. Disconnect With Data Transfer |
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