AM79C970A datasheet(69/219 Pages) AMD

69 / 219 page

P R E L I M I N A R Y

AMD

Am79C970A

The following figure illustrates the relationship between

the initialization base address, the initialization block,

the

receive

and

transmit

descriptor

ring

base

addresses, the receive and transmit descriptors and the

receive and transmit data buffers, when SSIZE32 is set

to ONE.

19436A-36

Initialization

Block

CSR1

CSR2

Rcv

Buff

RMD

Rcv Descriptor

Ring

•

1st

desc.

start

2nd

desc.

start

RMD

Xmt

Buff

TMD0

TMD1 TMD2 TMD3

Xmt Descriptor

Ring

•

1st

desc.

start

2nd

desc.

start

TMD0

Data

Buffer

Data

Buffer

Data

Buffer

Data

Buffer

Data

Buffer

Data

Buffer

PADR[31:0]

IADR[31:16]

IADR[15:0]

TLE RES RLE RES

MODE

PADR[47:32]

RES

LADRF[31:0]

LADRF[63:32]

RDRA[31:0]

TDRA[31:0]

Figure 33. 32-bit Software Model

Polling

If there is no network channel activity and there is no

pre- or post-receive or pre- or post-transmit activity be-

ing performed by the PCnet-PCI II controller, then the

PCnet-PCI II controller will periodically poll the current

receive and transmit descriptor entries in order to ascer-

tain their ownership. If the DPOLL bit in CSR4 is set,

then the transmit polling function is disabled.

A typical polling operation consists of the following: The

PCnet-PCI II controller will use the current receive de-

scriptor address stored internally to vector to the

appropriate Receive Descriptor Table Entry (RDTE). It

will then use the current transmit descriptor address

(stored internally) to vector to the appropriate Transmit

Descriptor Table Entry (TDTE). The accesses will be

made in the following order: RMD1, then RMD0 of the

current RDTE during one bus arbitration, and after that,

TMD1, then TMD0 of the current TDTE during a second

bus arbitration. All information collected during polling

activity will be stored internally in the appropriate CSRs,

if the OWN bit is set. (i.e. CSR18, CSR19, CSR20,

CSR21, CSR40, CSR42, CSR50, CSR52).

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