AM79C970A datasheet(42/219 Pages) AMD

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P R E L I M I N A R Y

Am79C970A

Master Bus Interface Unit

The master bus interface unit (BIU) controls the

acquisition of the PCI bus and all accesses to the

initialization block, descriptor rings and the receive and

transmit buffer memory. The table below shows the us-

age of PCI commands by the PCnet-PCI II controller in

master mode.

Table 3. Master Commands

C[3:0]

Command

Use

0000

Interrupt Acknowledge

Not Used

0001

Special Cycle

Not Used

0010

I/O Read

Not Used

0011

I/O Write

Not Used

0100

Reserved

0101

Reserved

0110

Memory Read

Read of the Initialization Block and Descriptor Rings

Read of the Transmit Buffer in Non-burst Mode

0111

Memory Write

Write to the Descriptor Rings and to the Receive Buffer

1000

Reserved

1001

Reserved

1010

Configuration Read

Not Used

1011

Configuration Write

Not Used

1100

Memory Read Multiple

Read of the Transmit Buffer in Burst Mode

1101

Dual Address Cycle

Not Used

1110

Memory Read Line

Read of the Transmit Buffer in Burst Mode

1111

Memory Write Invalidate

Not Used

Bus Acquisition

The PCnet-PCI II controller microcode will determine

when a DMA transfer should be initiated. The first step in

any PCnet-PCI II controller bus master transfer is to

acquire ownership of the bus. This task is handled by

synchronous logic within the BIU. Bus ownership is re-

quested with the

REQ signal and ownership is granted

by the arbiter through the

GNT signal.

Figure 12 shows the PCnet-PCI II controller bus

acquisition.

REQ is asserted and the arbiter returns

GNT while another bus master is transferring data. The

PCnet-PCI II controller waits until the bus is idle

(

FRAME and IRDY deasserted) before it starts driving

AD[31:0] and C/

BE[3:0] on clock 5. FRAME is asserted

at clock 5 indicating a valid address and command on

AD[31:0] and C/

BE[3:0]. The PCnet-PCI II controller

does not use address stepping which is reflected by

ADSTEP (bit 7) in the PCI Command register being

hardwired to ZERO.

In burst mode, the deassertion of

REQ depends on the

setting of EXTREQ (BCR18, bit 8). If EXTREQ is

cleared to ZERO ,

REQ is deasserted at the same time

FRAME is asserted. (The PCnet-PCI II controller

never performs more than one burst transaction within a

single bus mastership period). If EXTREQ is set to ONE,

the PCnet-PCI II controller does not deassert

REQ until

it starts the last data phase of the transaction.

Once asserted,

REQ remains active until GNT has be-

come active, independent of subsequent setting of the

STOP (CSR0, bit 2) or SPND (CSR5, bit 0). The asser-

tion of H_RESET or S_RESET, however, will cause

REQ to go inactive immediately.

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