AM79C970A datasheet(82/219 Pages) AMD

82 / 219 page

AMD

P R E L I M I N A R Y

Am79C970A

A system that wants to stop the clock during Magic

Packet mode should use one of the LED pins as an indi-

cator of Magic Packet frame detection. It should also

stop the clock after enabling Magic Packet mode, other-

wise PCI bus activity, including accessing CSR5 to set

MPMODE and possibly MPEN to a ONE, could be af-

fected. The clock should be restarted before Magic

Packet mode is disabled if MPEN is being cleared or the

clock must be restarted right after magic packet mode is

disabled if

SLEEP is being deasserted. Otherwise, the

receive FIFO may overflow if new frames arrive. The

network clock (XTAL1) must continue running at all

times while in Magic Packet mode.

MANCHESTER ENCODER/DECODER

The

integrated

Manchester

Encoder/Decoder

(MENDEC) provides the PLS (Physical Layer Signaling)

functions required for a fully compliant ISO 8802-3

(IEEE/ANSI 802.3) station. The MENDEC provides the

encoding function for data to be transmitted on the net-

work using the high accuracy on-board oscillator, driven

by either the crystal oscillator or an external CMOS level

compatible clock. The MENDEC also provides the de-

coding function from data received from the network.

The MENDEC contains a Power On Reset (POR) cir-

cuit, which ensures that all analog portions of the

PCnet-PCI II controller are forced into their correct state

during power up, and prevents erroneous data trans-

mission and/or reception during this time.

External Crystal Characteristics

When using a crystal to drive the oscillator, the following

crystal specification may be used to ensure less than

±0.5 ns jitter at DO±:

Table 7. Crystal Characteristics

Parameter

Min

Nom

Max

Units

1. Parallel Resonant Frequency

MHz

2. Resonant Frequency Error

–50

+50

PPM

3. Change in Resonant Frequency

With Respect To Temperature (0 – 70 C)*

–40

+40

PPM

4. Crystal Load Capacitance

5. Motional Crystal Capacitance (C1)

0.022

6. Series Resistance

ohm

7. Shunt Capacitance

7pF

8. Drive Level

TBD

* Requires trimming specification, not trim is 50 PPM total.

External Clock Drive Characteristics

When driving the oscillator from a CMOS level

external clock source, XTAL2 must be left floating

(unconnected). An external clock having the following

characteristics must be used to ensure less than

±0.5 ns

jitter at DO

±.

Table 8. External Clock Source Characteristics

Clock Frequency:

20 MHz

±0.01%

Rise/Fall Time (tR/tF):

<= 6 ns from 0.5 V to VDD –0.5 V

XTAL1 HIGH/LOW Time (tHIGH/tLOW):

20 ns min.

XTAL1 Falling Edge to Falling Edge Jitter:

±0.2 ns at 2.5 V input (VDD/2)

MENDEC Transmit Path

The transmit section encodes separate clock and NRZ

data input signals into a standard Manchester encoded

serial bit stream. The transmit outputs (DO

±) are de-

signed to operate into terminated transmission lines.

When operating into a 78

Ω terminated transmission

line, the transmit signaling meets the required output

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