AM79C970A datasheet(91/219 Pages) AMD

91 / 219 page

P R E L I M I N A R Y

AMD

Am79C970A

19436A-42

PCnet–PCI II

EROE

ERACLK

ERA[7:0]

ERD[7:0]

Expansion ROM

A[15:8]

A[7:0]

D[7:0]

Latch

Figure 39. Expansion ROM Interface

The PCnet-PCI II controller will always read four bytes

for every host Expansion ROM read access. The inter-

face to the Expansion ROM runs synchronous to the

PCI bus interface clock. The PCnet-PCI II controller will

start the read operation to the Expansion ROM by driv-

ing the upper 8-bits of the Expansion ROM address on

ERA[7:0]. This happens in the same clock cycle that the

device claims the transfer by asserting

DEVSEL. One

clock later,

EROE is asserted and ERACLK goes high to

allow latching of the upper address bits externally. The

upper portion of the Expansion ROM address will be the

same for all four byte read cycles. ERACLK is asserted

for one clock. ERA[7:0] are driven with the upper 8-bits

of the Expansion ROM address for one more clock cycle

after ERACLK goes low. Next, the PCnet-PCI II control-

ler starts driving the lower 8 bits of the Expansion ROM

address on ERA[7:0].

The time the PCnet-PCI II controller waits for data to be

valid is programmable. ROMTMG (BCR18, bits 15–12)

defines the time from when the PCnet-PCI II controller

drives ERA[7:0] with the lower 8-bits of the Expansion

ROM address to when the PCnet-PCI II controller

latches in the data on the ERD[7:0] inputs. The register

value specifies the time in number of clock cycles. When

ROMTMG is set to Nine (the default value), ERD[7:0] is

sampled with the next rising edge of CLK nine clock cy-

cles after ERA[7:0] was driven with a new address

value. The clock edge that is used to sample the data is

also the clock edge that generates the next Expansion

ROM address. Only the first three bytes of Expansion

ROM data are stored in holding registers. The fourth

byte is passed directly from the ERD[7:0] inputs to the

AD[31:24] outputs. One clock cycle after the last data

byte is available, PCnet-PCI II controller asserts

TRDY.

Two clock cycles after the data is transferred on the PCI

bus,

EROE is deasserted.

The access time for the Expansion ROM device (tACC)

can be calculated by subtracting the clock to output de-

lay for the ERA[7:0] outputs (tVAL(ERA)) and the input to

clock setup time for the ERD[7:0] inputs (tSU(ERD)) from

the time defined by ROMTMG:

tACC

≤ ROMTMG* clock period – t

VAL

(ERA) – tSU(ERD)

For an adapter card application, the value used for clock

period should be 30 ns to guarantee correct interface

timing at the maximum clock frequency of 33 MHz.

AM79C970A 数据表(PDF) 91 Page - Advanced Micro Devices

AM79C970A 数据表(HTML) 91 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载