AM79C970A datasheet(59/219 Pages) AMD

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P R E L I M I N A R Y

AMD

Am79C970A

19436A-29

FRAME

CLK

IRDY

TRDY

DEVSEL

REQ

GNT

PAR

DEVSEL is sampled

MD1

0000

0110

PAR

DATA

MD0

0000

0110

PAR

2345678

Figure 26. Descriptor Ring Read In Non-Burst Mode

During descriptor write accesses, only the byte lanes

which need to be written are enabled.

If buffer chaining is used, accesses to the descriptors of

all intermediate buffers consist of only one data transfer

to return ownership of the buffer to the system. When

SWSTYLE (BCR20, bits 7–0) is cleared to ZERO (i.e.

the descriptor entries are organized as 16-bit software

structures), the descriptor access will write a single byte.

When SWSTYLE (BCR20, bits 7–0) is set to ONE, TWO

or THREE (i.e. the descriptor entries are organized as

32-bit software structures), the descriptor access will

write a single word. On all single buffer transmit or re-

ceive descriptors, as well as on the last buffer in chain,

writes to the descriptor consist of two data transfers. The

first one writing a DWord containing status information.

The second data transfer writing a byte (SWSTYLE

cleared to ZERO) or otherwise a word containing addi-

tional status and the ownership bit (i.e. MD1[31]).

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