AM79C970A datasheet(74/219 Pages) AMD

74 / 219 page

AMD

P R E L I M I N A R Y

Am79C970A

interFrame gap to be generated, leading to a potential

reception failure of a subsequent frame. To enhance

system robustness the following optional measures,as

specified in 4.2.8, are recommended when InterFrame

Spacing Part 1 is other than ZERO:

1. Upon completing a transmission, start timing the

interpacket gap, as soon as transmitting and carrier

Sense are both false.

2. When timing an interFrame gap following reception,

reset the interFrame gap timing if carrier Sense be-

comes true during the first 2/3 of the interFrame gap

timing interval. During the final 1/3 of the interval the

timer shall not be reset to ensure fair access to the

medium. An initial period shorter than 2/3 of the

interval is permissible including ZERO.”

The MAC engine implements the optional receive two

part deferral algorithm, with a first part inter-frame-

spacing time of 6.0

µs. The second part of the

inter-frame-spacing interval is therefore 3.6

µs.

The PCnet-PCI II controller will perform the two part de-

ferral algorithm as specified in Section 4.2.8 (Process

Deference). The Inter Packet Gap (IPG) timer will start

timing the 9.6

µs InterFrameSpacing after the receive

carrier is deasserted. During the first part deferral (Inter-

Frame Spacing Part1 – IFS1) the PCnet-PCI II control-

ler will defer any pending transmit frame and respond to

the receive message. The IPG counter will be cleared to

ZERO continuously until the carrier deasserts, at which

point the IPG counter will resume the 9.6

µs count once

again. Once the IFS1 period of 6.0

µs has elapsed, the

PCnet-PCI II controller will begin timing the second part

deferral (Inter-Frame Spacing Part2 – IFS2) of 3.6

µs.

Once IFS1 has completed, and IFS2 has commenced,

the PCnet-PCI II controller will not defer to a receive

frame if a transmit frame is pending. This means that the

PCnet-PCI II controller will not attempt to receive the re-

ceive frame, since it will start to transmit, and generate a

collision at 9.6

µs. The PCnet-PCI II controller will com-

plete the preamble (64-bit) and jam (32-bit) sequence

before ceasing transmission and invoking the random

backoff algorithm.

This transmit two part deferral algorithm is implemented

as an option which can be disabled using the DXMT2PD

bit in CSR3. Two part deferral after transmission is

useful for ensuring that severe IPG shrinkage cannot

occur in specific circumstances, causing a transmit

message to follow a receive message so closely as to

make them indistinguishable.

During the time period immediately after a transmission

has been completed, the external transceiver (in the

case of a standard AUI connected device), should

generate the SQE Test message (a nominal 10 MHz

burst of 5–15 Bit Times duration) on the CI

± pair (within

0.6–1.6

µs after the transmission ceases). During the

time period in which the SQE Test message is expected

the PCnet-PCI II controller will not respond to receive

carrier sense.

See ANSI/IEEE Std 802.3-1990 Edition, 7.2.4.6 (1):

“At the conclusion of the output function, the DTE opens

a time window during which it expects to see the

signal_quality_error signal asserted on the Control

In circuit. The time window begins when the

CARRIER_STATUS becomes CARRIER_OFF. If exe-

cution of the output function does not cause

CARRIER_ON to occur, no SQE test occurs in the DTE.

The duration of the window shall be at least 4.0

µs but no

more than 8.0

µs. During the time window the Carrier

Sense Function is inhibited.”

The PCnet-PCI II controller implements a carrier sense

“blinding” period of 4.0

µs length starting from the

deassertion of carrier sense after transmission. This ef-

fectively means that when transmit two part deferral is

enabled (DXMT2PD is cleared) the IFS1 time is from

µs to 6 µs after a transmission. However, since IPG

shrinkage below 4

µs will rarely be encountered on a

correctly configured network, and since the fragment

size will be larger than the 4

µs blinding window, the IPG

counter will be reset by a worst case IPG shrinkage/frag-

ment scenario and the PCnet-PCI II controller will defer

its transmission. If carrier is detected within the 4.0 to

6.0

µs IFS1 period, the PCnet-PCI II controller will not

restart the “blinding” period, but only restart IFS1.

Collision Handling

Collision detection is performed and reported to

the MAC engine by the integrated Manchester

Encoder/Decoder (MENDEC).

If a collision is detected before the complete preamble/

SFD sequence has been transmitted, the MAC Engine

will complete the preamble/SFD before appending the

jam sequence. If a collision is detected after the pream-

ble/SFD has been completed, but prior to 512 bits being

transmitted, the MAC Engine will abort the transmis-

sion, and append the jam sequence immediately. The

jam sequence is a 32-bit all ZEROs pattern.

The MAC Engine will attempt to transmit a frame a total

of 16 times (initial attempt plus 15 retries) due to normal

collisions (those within the slot time). Detection of colli-

sion will cause the transmission to be re-scheduled to a

time determined by the random backoff algorithm. If a

single retry was required, the ONE bit will be set in the

transmit frame status. If more than one retry was re-

quired, the MORE bit will be set. If all 16 attempts experi-

enced collisions, the RTRY bit will be set (ONE and

MORE will be clear), and the transmit message will be

flushed from the FIFO. If retries have been disabled by

setting the DRTY bit in CSR15, the MAC Engine will

abandon transmission of the frame on detection of the

first collision. In this case, only the RTRY bit will be set

and the transmit message will be flushed from the FIFO.

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