AM79C970A datasheet(60/219 Pages) AMD

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AMD

P R E L I M I N A R Y

Am79C970A

19436A-30

FRAME

CLK

IRDY

TRDY

DEVSEL

REQ

GNT

234567

MD1

0000

0110

PAR

DATA

PAR

DEVSEL is sampled

Figure 27. Descriptor Ring Read In Burst Mode

The settings of SWSTYLE (BCR20, bits 7–0) and

BWRITE (BCR18, bit 5) affect the way the PCnet-PCI II

controller performs descriptor write operations.

When SWSTYLE is set to ZERO, ONE or TWO, all

descriptor write operations are performed in non-burst

mode. The setting of BWRITE has no effect in

this configuration.

When SWSTYLE is set to THREE, the descriptor entries

are ordered to allow burst transfers. The PCnet-PCI II

controller will perform all descriptor write operations in

burst mode, if BWRITE is set to ONE.

A write transaction to the descriptor ring entries is the

only case where the PCnet-PCI II controller inserts a

wait state when being the bus master. Every data phase

in non-burst and burst mode is extended by one clock

cycle, during which

IRDY is deasserted.

Table 5. Descriptor Write Sequence

SWSTYLE

BWRITE

BCR20[7:0]

BCR18[5]

AD Bus Sequence

Address = XXXX XX04h

Data = MD2[15:0], MD1[15:0]

Idle

Address = XXXX XX00h

Data = MD1[31:24]

1,2

Address = XXXX XX08h

Data = MD2[31:0]

Idle

Address = XXXX XX04h

Data = MD1[31:16]

Address = XXXX XX00h

Data = MD2[31:0]

Idle

Address = XXXX XX04h

Data = MD1[31:16]

Address = XXXX XX00h

Data = MD2[31:0]

Data = MD1[31:16]

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