AM79C970A datasheet(101/219 Pages) AMD

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AMD

101

Am79C970A

RST

INTA

CLK

GNT

REQ

AD[31:0]

BE[3:0]

IDSEL

FRAME

IRDY

TRDY

DEVSEL

STOP

LOCK

PERR

SERR

PAR

NOUT

FFFFFFFF

0000FFFF

19436A-47

Figure 1. NAND Tree Waveform

Reset

There are three different types of RESET operations

that may be performed on the PCnet-PCI II controller

device, H_RESET, S_RESET and STOP. These names

have been used throughout the document. The follow-

ing is a description of each type of RESET operation.

H_RESET

Hardware Reset (H_RESET) is a PCnet-PCI II control-

ler reset operation that has been created by the proper

assertion of the

RST pin of the PCnet-PCI II controller

device. When the minimum pulse width timing as speci-

fied in the

RST pin description has been satisfied, then

an internal reset operation will be performed.

H_RESET will program most of the CSR and BCR regis-

ters to their default value. Note that there are several

CSR and BCR registers that are undefined after

H_RESET. See the sections on the individual registers

for details. H_RESET will clear all registers in the

PCI configuration space. H_RESET will cause the

microcode program to jump to its reset state. Following

the end of the H_RESET operation, the PCnet-PCI II

controller will attempt to read the EEPROM device

through the EEPROM Microwire interface. H_RESET

resets the T-MAU into the Link Fail state.

S_RESET

Software Reset (S_RESET) is a PCnet-PCI II controller

reset operation that has been created by a read access

to the Reset register which is located at offset 14h in

Word I/O mode or offset 18h in DWord I/O mode from

the PCnet-PCI II controller I/O or memory mapped I/O

base address.

S_RESET will reset all of or some portions of CSR0, 3,

4, 15, 80, 100 and 124 to default values. For the identity

of individual CSRs and bit locations that are affected by

S_RESET, see the individual CSR register descriptions.

S_RESET will not affect any PCI configuration space

locations. With the exception of DWIO (BCR18, bit 7)

S _RESET will not affect any of the BCR register values.

S_RESET will cause the microcode program to jump to

its reset state. Following the end of the S_RESET op-

eration, the PCnet-PCI II controller will not attempt to

read the EEPROM device. S_RESET does not affect

the status of the T-MAU. After S_RESET, the host must

perform a full re-initialization of the PCnet-PCI II control-

ler before starting network activity.

S_RESET will clear DWIO (BCR18, bit 7) and the

PCnet-PCI II controller will be in 16-bit I/O mode after

the reset operation. A DWord write operation to the RDP

(I/O offset 10h) must be performed to set the device into

32-bit I/O mode.

S_RESET will cause

REQ to deassert immediately.

STOP (CSR0, bit 2) or SPND (CSR5, bit 0) can be used

to terminate any pending bus mastership request in an

orderly sequence.

S_RESET terminates all network activity abruptly. The

host can use the suspend mode (SPND, CSR5, bit 0) to

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