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AM79C978VC/W 数据表(PDF) 186 Page - Advanced Micro Devices |
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AM79C978VC/W 数据表(HTML) 186 Page - Advanced Micro Devices |
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186 / 261 page  186 Am79C978 HPR26: HomePNA PHY Event Status (Register 26) Table 58. HPR26: HomePNA PHY Event Status (Register 26) HPR27: HomePNA PHY Event Status (Register 27) The Event Status register reports the state of each event source. Any bit may be written and so facilitate software-stimulated event testing. Table 59. HPR27: HomePNA PHY Event Status (Register 27) HPR28: HomePNA PHY ISBI Control (Register 28) Table 60. HPR8: HomePNA PHY ISBI Control (Register 28) Bits Mnemonic Description Read/ Write Default Hex Soft Reset PHY_Event Status 15:10 Reserved R0 0 9RxPCOM Indicates a valid RxPCOM. An access to the RxCOM MSB Register 21 will clear this bit. R0 0 8TxPCOM Indicates a valid TxPCOM. Any access to the TxCOM registers (Registers 18 and 19) will clear this bit. R0 0 7:4 Reserved Reads will produce undefined results. R 3 Packet Received Status is cleared by writing a 0. R/W 0 0 2 Packet Transmitted Status is cleared by writing a 0. R/W 0 0 1 Remote Command Received A valid remote command was received. Status is cleared by writing a 0. R/W 0 0 0 Remote Command Sent A remote command has been sent. Status is cleared by writing a 0. R/W 0 0 Bits Mnemonic Description Read/ Write Default Hex Soft Reset AID_CTRL 15:8 AID_INTERVAL This value defines the number of TCLKs (116.6 ns) separating AID symbols. R/W 14 14 7:0 AID_ISBI This value defines the number of TCLKs (116.6 ns) separating AID symbol 0. R/W 40 40 Bits Mnemonic Description Read/ Write Default Hex Soft Reset ISBI_CTRL 15:8 ISBI_SLOW This value defines the number of TCLKs (116.6 ns) separating data pulses for Symbol 0 in low speed mode. R/W 2C 2C 7:0 ISBI_FAST This value defines the number of TCLKs (116.6 ns) separating data pulses for Symbol 0 in high speed mode. R/W 1C 1C |
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