AM79C978VCSLASHW datasheet(195/261 Pages) AMD

195 / 261 page

Am79C978

195

TBR16: 10BASE-T INTERRUPT Status and Enable

The Interrupt bits indicate when there is a change in the

Link Status, Duplex Mode, Auto-Negotiation status, or

Speed status. Register 16 contains the interrupt status

and interrupt enable bits. The status is always updated

whether or not the interrupt enable bits are set. When

an interrupt occurs, the system will need to read the in-

terrupt register to clear the status bits and determine

the course of action needed. See Table 74.

Table 74.

TBR16: 10BASE-T INTERRUPT Status and Enable Register (Register 16)

Note:

1. All bits, except bit 13, are cleared on read (COR). The register must be read twice to see if it has been cleared.

Bit(s)

Name

Description

Read/

Write

H/W or Soft

Reset

15:14

Reserved

Interrupt Test Enable

(Note 1)

1 = When this bit is set, setting bits 12:9 of this register

will cause a condition that will set bits 4:1

accordingly. The effect is to test the register bits with

a forced interrupt condition.

0 = Bits 4:1 are only set if the interrupt condition (if any

bits in 12:9 are set) occurs.

R/W

Link Status Change

Enable

1 = Link Status Change enable

0 = This interrupt is masked

R/W

Duplex Mode Change

Enable

1 = Duplex Mode Change enable

0 = This interrupt is masked

R/W

Auto-Neg Change

Enable

1 = Auto-Negotiation Change enable

0 = This interrupt is masked

R/W

Speed Change

Enable

1 = Speed Change enable

0 = This interrupt is masked

R/W

Global

Enable

1= Global Interrupt enable

0 = This interrupt is masked

R/W

7:5

Reserved

Link Status Change

1 = Link Status has changed on a port

0 = No change in Link Status

RO,

Duplex Mode Change

1 = Duplex Mode has changed on a port

0 = No change in Duplex mode

RO,

Auto-Negotiation Change

1 = Auto-Neg status has changed on a port

0 = No change in Auto-Neg status

RO,

Speed Change

1 = Speed status has changed on a port

0 = No change

RO,

Global

1 = Indicates a change in status of any of the above

interrupts

0 = Indicates no change in Interrupt Status

RO,

AM79C978VC/W 数据表(PDF) 195 Page - Advanced Micro Devices

AM79C978VC/W 数据表(HTML) 195 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载

链接网址

AM79C978VC/W 数据表(PDF) 195 Page - Advanced Micro Devices

AM79C978VC/W 数据表(HTML) 195 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表 下载

链接网址

数据表下载