AM79C978VCSLASHW datasheet(196/261 Pages) AMD

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196

Am79C978

TBR17: 10BASE-T PHY Control/Status Register

(Register 17)

This register is used to control the configuration of the

10 Mbps PHY unit of the Am79C978 home networking

device. See Table 75.

Table 75.

TBR17: 10BASE-T PHY Control/Status Register (Register 17)

Note:

1. For these loopback paths, the data is also transmitted out of the MDI pins (TX±).

Bits

Name

Description

Read/Write

H/W

Reset

Soft Reset

Reserved

R/W

Retains

Value

Reserved

R/W

Retains

Value

Force Link Good

Enable

1 = link status forced to link up state

0 = link status is determined by the device

R/W

Disable Link Pulse

1 = Link pulses sent from the

10BASE-T transmitter are suppressed

R/W

SQE_TEST Disable

1 = Disables the SQE heartbeat which occurs

after each 10BASE-T transmission

0 = The heart beat assertion occurs on the

COL pin approximately 1 µs after transmission

and for a duration of 1 µs.

R/W

Reserved

R/W

Jabber Detect Disable

1 = disable jabber detect

0 = enable jabber detect

R/W

8:7

Reserved

R/W

Receive Polarity

Reversed

1 = Receive polarity of the 10BASE-T receiver

is reversed

0 = Receive polarity is correct

Auto Receive Polarity

Correction Disable

1 = polarity correction circuit is disabled for

10BASE-T

0 = Self correcting polarity circuit is enabled

R/W

Extended Distance

Enable

1 = 10BASE-T receive squelch thresholds are

reduced to allow reception of frames which are

greater than 100 meters

0 = Squelch thresholds are set for standard

distance of 100 meters

R/W

TX_DISABLE

1 = TX± outputs not active for 10BASE-T. TX±

outputs to logical “0” for PECL.

0 = Transmit valid data

R/W

TX_CRS_EN

1 = CRS is asserted when transmit or receive

medium is active

0 = CRS is asserted when receive medium is

active

Reserved

PHY Isolated

1 = Internal PHY is isolated

0 = Internal PHY is enabled

0/1

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