AM79C978VCSLASHW datasheet(202/261 Pages) AMD

202 / 261 page

202

Am79C978

BPE

Bus Parity Error is set by the

Am79C978 controller when a par-

ity error occurred on the bus inter-

face during data transfers to a

receive buffer. BPE is valid only

when ENP, OFLO, or BUFF are

set. The Am79C978 controller will

only set BPE when the advanced

parity error handling is enabled

by setting APERREN (BCR20, bit

10) to 1. BPE is set by the

Am79C978

controller

and

cleared by the host.

This bit does not exist when the

Am79C978

controller

pro-

grammed to use 16-bit software

structures for the descriptor ring

entries (BCR20, bits 7-0, SW-

STYLE is cleared to 0).

PAM

Physical Address Match is set by

the Am79C978 controller when it

accepts the received frame due

to a match of the frame’s destina-

tion address with the content of

the physical address register.

PAM is valid only when ENP is

set. PAM is set by the Am79C978

controller and cleared by the

host.

This bit does not exist when the

Am79C978

controller

pro-

grammed to use 16-bit software

structures for the descriptor ring

entries (BCR20, bits 7-0, SW-

STYLE is cleared to 0).

LAFM

Logical Address Filter Match is

set by the Am79C978 controller

when it accepts the received

frame based on the value in the

logical

address

filter

LAFM is valid only when ENP is

set.

LAFM

set

the

Am79C978

controller

and

cleared by the host.

Note that if DRCVBC (CSR15, bit

14) is cleared to 0, only BAM, but

not LAFM will be set when a

Broadcast

frame

received,

even if the Logical Address Filter

is programmed in such a way that

a Broadcast frame would pass

the hash filter. If DRCVBC is set

to 1 and the Logical Address Fil-

ter is programmed in such a way

that a Broadcast frame would

pass the hash filter, LAFM will be

set on the reception of a Broad-

cast frame.

This bit does not exist when the

Am79C978

controller

pro-

grammed to use 16-bit software

structures for the descriptor ring

entries (BCR20, bits 7-0, SW-

STYLE is cleared to 0).

BAM

Broadcast Address Match is set

the

Am79C978

controller

when it accepts the received

frame, because the frame’s desti-

nation address is of the type

’Broadcast.’ BAM is valid only

when ENP is set. BAM is set by

the Am79C978 controller and

cleared by the host.

This bit does not exist when the

Am79C978

controller

pro-

grammed to use 16-bit software

structures for the descriptor ring

entries (BCR20, bits 7-0, SW-

STYLE is cleared to 0).

19-16 RES

Reserved locations. These loca-

tions should be read and written

as zeros.

15-12 ONES

These four bits must be written as

ones. They are written by the host

and

unchanged

the

Am79C978 controller.

11-0

BCNT

Buffer Byte Count is the length of

the buffer pointed to by this de-

scriptor, expressed as the two’s

complement of the length of the

buffer. This field is written by the

host

and

unchanged

the

Am79C978 controller.

RMD2

Bit

Name

Description

ZERO

This

field

reserved.

The

Am79C978 controller will write a

zero to this location.

30-16 RFRTAG

Receive Frame Tag. Indicates

the Receive Frame Tag applied

from the EADI interface. This field

is user defined and has a default

value of all zeros. When RX-

FRTG (CSR7, bit 14) is set to 0,

AM79C978VC/W 数据表(PDF) 202 Page - Advanced Micro Devices

AM79C978VC/W 数据表(HTML) 202 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载

链接网址

AM79C978VC/W 数据表(PDF) 202 Page - Advanced Micro Devices

AM79C978VC/W 数据表(HTML) 202 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表 下载

链接网址

数据表下载