AM79C978VCSLASHW datasheet(204/261 Pages) AMD

204 / 261 page

204

Am79C978

TMD0

Bit

Name

Description

31-0

TBADR

Transmit Buffer address. This

field contains the address of the

transmit buffer that is associated

with this descriptor.

TMD1

Bit

Name

Description

OWN

This bit indicates whether the de-

scriptor entry is owned by the

host (OWN = 0) or by the

Am79C978 controller (OWN = 1).

The host sets the OWN bit after

filling the buffer pointed to by the

descriptor entry. The Am79C978

controller clears the OWN bit af-

ter transmitting the contents of

the buffer. Both the Am79C978

controller and the host must not

alter a descriptor entry after it has

relinquished ownership.

ERR

ERR is the OR of UFLO, LCOL,

LCAR, RTRY or BPE. ERR is set

by the Am79C978 controller and

cleared by the host. This bit is set

in the current descriptor when the

error occurs and, therefore, may

be set in any descriptor of a

chained buffer transmission.

ADD_FCS

ADD_FCS dynamically controls

the generation of FCS on a frame

by frame basis. This bit should be

set with the ENP bit. However, for

backward compatibility, it is rec-

ommended that this bit be set for

every descriptor of the intended

frame. When ADD_FCS is set,

the state of DXMTFCS is ignored

and transmitter FCS generation is

activated. When ADD_FCS is

cleared to 0, FCS generation is

controlled by DXMTFCS. When

APAD_XMT (CSR4, bit 11) is set

to 1, the setting of ADD_FCS has

no effect. ADD_FCS is set by the

host, and is not changed by the

Am79C978 controller. This is a

reserved bit in the C-LANCE

(Am79C90) controller.

MORE/LTINT Bit

always

functions

MORE. The value of MORE is

written by the Am79C978 control-

ler and is read by the host. When

LTINTEN is cleared to 0 (CSR5,

bit 14), the Am79C978 controller

will never look at the contents of

bit 28, write operations by the

host have no effect. When LTINT-

EN is set to 1 bit 28 changes its

function to LTINT on host write

operations and on Am79C978

controller read operations.

MORE indicates that more than

one retry was needed to transmit

a frame. The value of MORE is

written by the Am79C978 control-

ler. This bit has meaning only if

the ENP bit is set.

LTINT

LTINT is used to suppress inter-

rupts after successful transmis-

sion on selected frames. When

LTINT is cleared to 0 and ENP is

set to 1, the Am79C978 controller

will not set TINT (CSR0, bit 9) af-

ter a successful transmission.

TINT will only be set when the

last descriptor of a frame has

both LTINT and ENP set to 1.

When LTINT is cleared to 0, it will

only cause the suppression of in-

terrupts for successful transmis-

sion. TINT will always be set if the

transmission has an error. The

LTINTEN overrides the function

of TOKINTD (CSR5, bit 15).

ONE

ONE indicates that exactly one

retry was needed to transmit a

frame. ONE flag is not valid when

LCOL is set. The value of the

ONE

bit

written

the

Am79C978 controller. This bit

has meaning only if the ENP bit is

set.

DEF

Deferred

indicates

that

the

Am79C978 controller had to de-

fer while trying to transmit a

frame. This condition occurs if the

channel

busy

when

the

Am79C978 controller is ready to

transmit. DEF is set by the

Am79C978

controller

and

cleared by the host.

STP

Start of Packet indicates that this

is the first buffer to be used by the

Am79C978

controller

for

this

frame. It is used for data chaining

AM79C978VC/W 数据表(PDF) 204 Page - Advanced Micro Devices

AM79C978VC/W 数据表(HTML) 204 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载

链接网址

AM79C978VC/W 数据表(PDF) 204 Page - Advanced Micro Devices

AM79C978VC/W 数据表(HTML) 204 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表 下载

链接网址

数据表下载