AR0330 datasheet(8/77 Pages) ONSEMI

8 / 77 page

AR0330_DS Rev. U Pub. 4/15 EN

©Semiconductor Components Industries, LLC,2015.

AR0330: 1/3-Inch CMOS Digital Image Sensor

Working Modes

Figure 2:

Typical Configuration: Serial Four-Lane HiSPi Interface

Notes:

1. All power supplies must be adequately decoupled. ON Semiconductor recommends having 1.0F

and 0.1F decoupling capacitors for every power supply. If space is a concern, then priority must be

given in the following order: VAA, VAA_PIX, VDD_PLL, VDD_IO, and VDD. Actual values and results may

vary depending on layout and design considerations.

2. To allow for space constraints, ON Semiconductor recommends having 0.1F decoupling capacitor

inside the module as close to the pads as possible. In addition, place a 10F capacitor for each sup-

ply off-module but close to each supply.

3. ON Semiconductor recommends a resistor value of 1.5k, but a greater value may be used for

slower two-wire speed.

4. The pull-up resistor is not required if the controller drives a valid logic level on SCLK at all times.

5. ON Semiconductor recommends that analog power planes are placed in a manner such that cou-

pling with the digital power planes is minimized.

6. TEST pin should be tied to DGND.

7. Set High_VCM (R0x306E[9]) to 0 (default) to use the VDD_HiSPi_TX in the range of 0.4 – 0.8V. Set

High_VCM to 1 to use a range of 1.7 – 1.9V.

8. The package pins or die pads used for the MIPI data and clock as well as the parallel interface must

be left floating.

9. The VDD_MIPI package pin and sensor die pad should be connected to a 2.8V supply as VDD_MIPI is

tied to the VDD_PLL supply both in the package routing and also within the sensor die itself.

10. If the SHUTTER or FLASH pins or pads are not used, then they must be left floating.

11. If the TRIGGER or OE_BAR pins or pads are not used, then they should be tied to DGND.

12. The GND_SLVS pad must be tied to DGND. It is connected this way in the CLCC and CSP packages.

VDD_IO

VDD_HiSPi

VDD_PLL

VDD

VAA

VDD

VAA

VAA_PIX

Master clock

(6–27

MHz)

SCLK

SDATA

RESET_BAR

TEST

EXTCLK

DGND

GND_SLVS

AGND

Digital

ground

Analog

ground

Digital

Core

power1

HiSPi

power1

Analog

power1

controller

From

controller

VDD_IO

PLL

power1

Digital

I/O

power1

Analog

power1

VAA_PIX

SLVSC_N

SLVSC_P

SLVS0_P

SLVS0_N

SLVS1_P

SLVS1_N

SLVS2_N

SLVS3_P

SLVS3_N

SADDR

FLASH

SHUTTER

1.o

μF

1.o

μF

1.o

μF

1.o

μF

1.o

μF

1.o

μF

0.1

μF

0.1

μF

0.1

μF

0.1

μF

0.1

μF

0.1

μF

OE_BAR

TRIGGER

(HiSPi-serial interface)

VDD_HiSPi_TX

1.o

μF 0.1μF

SLVS2_P

AR0330 数据表(PDF) 8 Page - ON Semiconductor

AR0330 数据表(HTML) 8 Page - ON Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77

数据表下载

链接网址

AR0330 数据表(PDF) 8 Page - ON Semiconductor

AR0330 数据表(HTML) 8 Page - ON Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77

数据表 下载

链接网址

数据表下载