AR0330 datasheet(10/77 Pages) ONSEMI

10 / 77 page

AR0330_DS Rev. U Pub. 4/15 EN

©Semiconductor Components Industries, LLC,2015.

AR0330: 1/3-Inch CMOS Digital Image Sensor

Working Modes

Figure 4:

Typical Configuration: Parallel Pixel Data Interface

Notes:

1. All power supplies must be adequately decoupled. ON Semiconductor recommends having 1.0F

and 0.1F decoupling capacitors for every power supply. If space is a concern, then priority must be

given in the following order: VAA, VAA_PIX, VDD_PLL, VDD_IO, and VDD. Actual values and results may

vary depending on layout and design considerations.

2. To allow for space constraints, ON Semiconductor recommends having 0.1F decoupling capacitor

inside the module as close to the pads as possible. In addition, place a 10F capacitor for each sup-

ply off-module but close to each supply.

3. ON Semiconductor recommends a resistor value of 1.5k, but a greater value may be used for

slower two-wire speed.

4. The pull-up resistor is not required if the controller drives a valid logic level on SCLK at all times.

5. ON Semiconductor recommends that analog power planes are placed in a manner such that cou-

pling with the digital power planes is minimized.

6. TEST pin should be tied to the ground.

7. The data and clock package pins or die pads used for the HiSPi and MIPI interface must be left float-

ing.

8. The VDD_MIPI package pin and sensor die pad should be connected to a 2.8V supply as it is tied to

the VDD_PLL supply both in the package routing and also within the sensor die itself. HiSPi Power

Supplies (VDD_HiSPi and VDD_HiSPi_TX) can be tied to ground.

9. If the SHUTTER or FLASH pins or pads are not used, then they must be left floating.

10. If the TRIGGER or OE_BAR pins or pads are not used, then they should be tied to DGND.

VDD

Master clock

(6–27 MHz)

SADDR

SCLK

TEST

FRAME_VALID

DOUT [11:0]

EXTCLK

DGND

Digital

ground

Analog

ground

Digital

core

power1

controller

From

Controller

LINE_VALID

PIXCLK

RESET_BAR

VDD_IO

Digital

I/O

power1

VAA VAA_PIX

Analog

power1

PLL

power1

Analog

power1

VAA_PIX

VDD_IO

VDD_PLL

VDD

VAA

AGND

TRIGGER

SHUTTER

FLASH

1.0

μF

1.0

μF

1.0

μF

1.0

μF1.0μF

0.1

μF

0.1

μF

0.1

μF

0.1

μF

0.1

μF

SDATA

OE_BAR

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