AR0330 datasheet(33/77 Pages) ONSEMI

33 / 77 page

AR0330_DS Rev. U Pub. 4/15 EN

©Semiconductor Components Industries, LLC,2015.

AR0330: 1/3-Inch CMOS Digital Image Sensor

Sensor PLL

Dual Readout Paths

There are two readout paths within the sensor digital block.

Figure 18:

Sensor Dual Readout Paths

The sensor row timing calculations refers to each data-path individually. For example,

the sensor default configuration uses 1248 clocks per row (line_length_pck) to output

2304 active pixels per row. The aggregate clocks per row seen by the receiver will be 2496

clocks (1248 x 2 readout paths).

Parallel PLL Configuration

Figure 19:

PLL for the Parallel Interface

The parallel interface has a maximum output data-rate of 98MPixel/s.

The maximum output of the parallel interface is 98 Mpixel/s (CLK_OP). This will limit

the readout clock (CLK_PIX) to 49 Mpixel/s. The sensor will not use the FSERIAL, FSERI-

AL_CLK, or CLK_OP when configured to use the parallel interface.

Pixel Array

All Digital

Blocks

S erial Output

CLK_PIX

Pixel Rate = 2 x CLK_PIX

= # data lanes x CLK_OP (HiSPi or MIPI)

= CLK_OP (Parallel)

(MIPI or HiSPi)

All Digital

Blocks

1/2

pre_pll_clk_div

2(1-64)

pll_multiplier

58(32-384)

vt_sys_clk_div

1(1, 2, 4, 6, 8,

10, 12, 14, 16)

vt_pix_clk_div

6(4-16)

EXTCLK

6-27 MHz

CLK_PIX

(Max 49 Mpixels/s)

CLK_OP

(Max 98 Mpixels/s)

Fvco

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