AR0330 datasheet(36/77 Pages) ONSEMI

36 / 77 page

AR0330_DS Rev. U Pub. 4/15 EN

©Semiconductor Components Industries, LLC,2015.

AR0330: 1/3-Inch CMOS Digital Image Sensor

Pixel Output Interfaces

Parallel Interface

The parallel pixel data interface uses these output-only signals:

•FV

•LV

•PIXCLK

•DOUT[11:0]

The parallel pixel data interface is disabled by default at power up and after reset. It can

be enabled by programming R0x301A. Table 30 on page 36 shows the recommended

settings.

When the parallel pixel data interface is in use, the serial data output signals can be left

unconnected. Set reset_register[12] to disable the serializer while in parallel output

mode.

Output Enable Control

When the parallel pixel data interface is enabled, its signals can be switched asynchro-

nously between the driven and High-Z under pin or register control, as shown in

Table 29. OE_BAR pin is only available on the bare die version.

Configuration of the Pixel Data Interface

Fields in R0x301A are used to configure the operation of the pixel data interface. The

supported combinations are shown in Table 30.

Table 29:

Output Enable Control

OE_BAR Pin

Drive Signals R0x301A–B[6]

Description

Disabled

Interface High-Z

Disabled

Interface driven

Interface High-Z

Interface driven

Table 30:

Configuration of the Pixel Data Interface

Serializer

Disable

R0x301

A–B[12]

Parallel

Enable

R0x301A–B[7]

Standby

End-of-Frame

R0x301A–B[4]

Description

Power up default.

Serial pixel data interface and its clocks are enabled. Transitions to soft

standby are synchronized to the end of frames on the serial pixel data

interface.

Parallel pixel data interface, sensor core data output. Serial pixel data

interface and its clocks disabled to save power. Transitions to soft standby

are synchronized to the end of the current row readout on the parallel pixel

data interface.

Parallel pixel data interface, sensor core data output. Serial pixel data

interface and its clocks disabled to save power. Transitions to soft standby

are synchronized to the end of frames in the parallel pixel data interface.

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