AR0330 datasheet(21/77 Pages) ONSEMI

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AR0330_DS Rev. U Pub. 4/15 EN

©Semiconductor Components Industries, LLC,2015.

AR0330: 1/3-Inch CMOS Digital Image Sensor

Electrical Characteristics

4. A device must internally provide a hold time of at least 300 ns for the SDATA signal to bridge the

undefined region of the falling edge of SCLK.

5. The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of

the SCLK signal.

6. A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement

tSU;DAT 250 ns must then be met. This will automatically be the case if the device does not stretch

the LOW period of the SCLK signal. If such a device does stretch the LOW period of the SCLK signal, it

must output the next data bit to the SDATA line tr max + tSU;DAT = 1000 + 250 = 1250 ns (according

to the Standard-mode I2C-bus specification) before the SCLK line is released.

7. Cb = total capacitance of one bus line in pF.

Figure 9:

I/O Timing Diagram (Parallel Mode)

Table 15:

I/O Parameters

fEXTCLK = 24 MHz; VDD = 1.8V; VAA = 2.8V; VAA_PIX = 2.8V; VDD_PLL = 2.8V; Output load = 68.5pF; T

J = 60°C;

CLK_OP = 98 MPixel/s

Symbol

Definition

Conditions

Min

Max

Units

VIH

Input HIGH voltage

VDD_IO = 1.8V

1.4

VDD_IO + 0.3

VDD_IO = 2.8V

2.4

VIL

Input LOW voltage

VDD_IO = 1.8V

GND – 0.3

0.4

VDD_IO = 2.8V

GND – 0.3

0.8

IIN

Input leakage current

No pull-up resistor; VIN = VDD OR

DGND

– 20

A

VOH

Output HIGH voltage

At specified IOH

VDD_IO - 0.4V

–

VOL

Output LOW voltage

At specified IOL

–0.4

IOH

Output HIGH current

At specified VOH

––12

IOL

Output LOW current

At specified VOL

–9

IOZ

Tri-state output leakage current

–

A

Data[11:0]

FRAME_VALID/

LINE_VALID

FRAME_VALID leads LINE_VALID by 609 PIXCLKs.

FRAME_VALID trails

LINE_VALID by 16 PIXCLKs.

PIXCLK

*PLL disabled for tCP

EXTCLK

tCP

tEXTCLK

tRP

tFP

tPD

tPFH

tPLH

tPFL

tPLL

Pxl _0

Pxl _1

Pxl _2

Pxl _n

90%

10%

90%

10%

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