AR0330 datasheet(34/77 Pages) ONSEMI

34 / 77 page

AR0330_DS Rev. U Pub. 4/15 EN

©Semiconductor Components Industries, LLC,2015.

AR0330: 1/3-Inch CMOS Digital Image Sensor

Sensor PLL

Serial PLL Configuration

Figure 20:

PLL for the Serial Interface

The sensor will use op_sys_clk_div and op_pix_clk_div to configure the output clock per

lane (CLK_OP). The configuration will depend on the number of active lanes (1, 2, or 4)

configured. To configure the sensor protocol and number of lanes, refer to “Serial

Configuration” on page 40.

Table 25:

PLL Parameters for the Parallel Interface

Parameter

Symbol

Min

Max

Unit

External Clock

EXTCLK

MHz

VCO Clock

FVCO

384

768

MHz

Readout Clock

CLK_PIX

Mpixel/s

Output Clock

CLK_OP

Mpixel/s

Table 26:

Example PLL Configuration for the Parallel Interface

Parameter

Value

Output

FVCO

588 MHz (Max)

vt_sys_clk_div

vt_pix_clk_div

CLK_PIX

49 Mpixel/s (= 588 MHz / 12)

CLK_OP

98 Mpixel/s (= 588 MHz / 6)

Output pixel rate

98 MPixel/s

pre_pll_clk_div

2(1-64)

pll_multiplier

58(32-384)

vt_sys_clk_div

1(1, 2, 4, 6, 8,

10, 12, 14, 16)

vt_pix_clk_div

6(4-16)

EXTCLK

6-27 MHz

CLK_PIX

CLK_OP

Fvco

op_sys_clk_div

Constant - 1

op_pix_clk_div

12(8, 10, 12)

1/2

Fvco

FSERIAL

FSERIAL_CLK

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