AR0330 datasheet(16/77 Pages) ONSEMI

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AR0330_DS Rev. U Pub. 4/15 EN

©Semiconductor Components Industries, LLC,2015.

AR0330: 1/3-Inch CMOS Digital Image Sensor

Sensor Initialization

Notes:

1. External clock settling time is component-dependent, usually taking about 10 – 100 ms.

2. Hard reset time is the minimum time required after power rails are settled. In a circuit where Hard

reset is held down by RC circuit, then the RC time must include the all power rail settle time and

Xtal settle time.

3. It is critical that VDD_PLL is not powered up after the other power supplies. It must be powered

before or at least at the same time as the others. If the case happens that VDD_PLL is powered after

other supplies then sensor may have functionality issues and will experience high current draw on

this supply.

4. VDD_MIPI is tied to VDD_PLL in the both the CLCC and CSP packages and must be powered to 2.8 V.

The VDD_HiSPi and VDD_HiSPi_TX supplies do not need to be turned on if the sensor is configured

to use the MIPI or parallel interface.

Table 7:

Power-Up Sequence

Definition

Symbol

Min

Typ

Max

Unit

VDD_PLL, VDD_MIPI to VAA/VAA_PIX3

100

–

s

VAA/VAA_PIX to VDD

100

–

s

VDD to VDD_IO

100

–

s

External clock settling time

–

301

–ms

Hard Reset

––

Internal Initialization

150000

–

EXTCLKs

Internal Initialization

150000

–

EXTCLKs

PLL Lock Time

–

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