AR0330 datasheet(38/77 Pages) ONSEMI

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AR0330_DS Rev. U Pub. 4/15 EN

©Semiconductor Components Industries, LLC,2015.

AR0330: 1/3-Inch CMOS Digital Image Sensor

Pixel Output Interfaces

HiSPi Physical Layer

The HiSPi physical layer is partitioned into blocks of four data lanes and an associated

clock lane. Any reference to the PHY in the remainder of this document is referring to

this minimum building block.

The PHY will serialize a 10-, 12-, 14- or 16-bit data word and transmit each bit of data

centered on a rising edge of the clock, the second on the falling edge of clock. Figure 22

shows bit transmission. In this example, the word is transmitted in order of MSB to LSB.

The receiver latches data at the rising and falling edge of the clock.

Figure 22:

Timing Diagram

DLL Timing Adjustment

The specification includes a DLL to compensate for differences in group delay for each

data lane. The DLL is connected to the clock lane and each data lane, which acts as a

control master for the output delay buffers. Once the DLL has gained phase lock, each

lane can be delayed in 1/8 unit interval (UI) steps. This additional delay allows the user

to increase the setup or hold time at the receiver circuits and can be used to compensate

for skew introduced in PCB design.

If the DLL timing adjustment is not required, the data and clock lane delay settings

should be set to a default code of 0x000 to reduce jitter, skew, and power dissipation.

Figure 23:

Block Diagram of DLL Timing Adjustment

….

MSB

LSB

TxPost

1 UI

TxPre

delay

data _lane 0

data _lane 1 clock _lane 0 data _lane 2 data _lane 3

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