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ADE3700 数据表(PDF) 81 Page - STMicroelectronics |
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ADE3700 数据表(HTML) 81 Page - STMicroelectronics |
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81 / 89 page  81/89 ADE3700 DFT Block 2.21 DFT Block PWM_CTRL1 0x01A1 R/W [7:4] 0x0 Lock 2 nd order gain (power of 2) 0x0 = max 0x3 = typical 0xF = min. R/W [3:0] 0x0 Lock gain (power of 2) 0x0 = max 0x6 = typical 0xF = min. PWM_PERIOD_L 0x01A2 R/W [7:0] 0x0 Period-2 in free-running mode, in XCLKs PWM_PERIOD_H 0x01A3 R/W [7:0] PWM_DUTY_L 0x01A4 R/W [7:0] 0x0 Duty cycle of PWM in XCLKs PWM_DUTY_H 0x01A5 R/W [7:0] PWM_OVERLAP_L 0x01A6 R/W [7:0] 0x0 Non-overlap of PWMs in XCLKs PWM_OVERLAP_H 0x01A7 R/W [7:0] PWM_STEP_DELAY 0x01A8 R/W [7:0] 0x0 In smooth change mode, the number of cycles skipped before the period/duty registers are incremented/decremented PWM_CYCLES_PER_FRAME_L 0x01A9 R/W [7:0] 0x0 The number of cycles per frame in frame lock mode when not using the internally generated cycles per frame from a previous free-running mode PWM_CYCLES_PER_FRAME_H 0x01AA R/W [7:0] Table 34: DFT Registers (Sheet 1 of 3) Register Name Addr Mode Bits Default Description DFT_TEST_MODE 0x0F00 [7:4] Reserved R/W [3] 0x0 trigger video bus MFSR R/W [2] 0x0 enable output pin MFSR R/W [1] 0x0 clear output pin MFSR R/W [0] 0x0 output pin test override DFT_MUX_OUT_MODE 0x0F01 [7:6] Reserved R/W [5:0] 0x0 mux selector for output porta/b and syncs DFT_FLOP_OUT_MODE 0x0F02 [7:6] Reserved R/W [5:0] 0x0 mux selector for synchronous digital debug bus DFT_CLK_0UT_MODE 0x0F03 R/W [7:6] 0x0 divide-by selector for clocks to OCLK pin fout = selected clock / (2 ^ value) R/W [5:0] 0x0 mux selector for clocks to OCLK pin DFT_CLK_1_MODE 0x0F04 R/W [7:6] 0x0 divide-by selector for clocks to CLKOUT pin fout = selected clock / (2 ^ value) Table 33: PWM Registers (Sheet 2 of 2) Register Name Addr Mode Bits Default Description |
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