ADE3700 datasheet(18/89 Pages) STMICROELECTRONICS

18 / 89 page

Line Lock PLL

ADE3700

18/89

2.4

Line Lock PLL

The Line Lock PLL recovers a sample clock from an incoming hsync source. The response

characteristics of the line lock PLL can be adjusted for optimum response time and jitter filtering.

The phase of the sample clock can be digitally adjusted in steps of 289 ps (with a 27-MHz crystal).

The I2C interface of the line lock PLL is in the LLK_CTRL clock domain which must be active for

programming.

The PLL filter has three ranges with independent filter parameters. When the phase detector error

stays below a programmable threshold for a programmable number of input lines, the PLL filter

coefficients are changed. Any phase detector error above the programmed threshold will return the

filter to the appropriate level in one line. The operation is shown in Figure 3.

The digital loop filter is controlled by three parameters: MFACTOR, A and B. M_FACTOR is the

desired number of clocks per input line. The A and B parameters control the response of the 2nd

order digital filter. A and B are composed of a linear and exponential component designated by the

L and E suffix, respectively. The relationship of these numbers to the classic 2nd order damping and

natural frequency are as follows:

Damping = AL x 2(AE-12) x SQRT(5 x M_FACTOR / (BL x 2BE))

Natural Frequency = SQRT(M_FACTOR x 5 x BL x 2(BE-34))

ADC_OFFSET_B

0x0329

R/W

[7:0]

0x0

Offset Control, Blue Channel

ADC_GAIN_R

0x032A

R/W

[7:0]

0x0

Gain Control, Red Channel

ADC_GAIN_G

0x032B

R/W

[7:0]

0x0

Gain Control, Green Channel

ADC_GAIN_B

0x032C

R/W

[7:0]

0x0

Gain Control, Blue Channel

Figure 3: Line Lock PLL

Table 6: ADC Registers (Sheet 2 of 2)

Addr.

Mode

Bits

Default

Description

Fast

Slow

Lock

Error > SLOW_TOL

Error <= SLOW_TOL for

more than LOCK_LINE_NB

Error > LOCK_TOL

more than SLOW_LINE_NB

of lines

Error <= LOCK_TOL for

of lines

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