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ADE3700 数据表(PDF) 43 Page - STMicroelectronics |
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ADE3700 数据表(HTML) 43 Page - STMicroelectronics |
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43 / 89 page ![]() 43/89 ADE3700 LCD Scaler SCL_ORIGHPOS_0 0x0A0A R/W [7:0] 0x0 2’s complement, signed number 27-bit horizontal position of the first output pixel =(-dest_hpos * scalefactor_h) >> 5 SCL_ORIGHPOS_1 0x0A0B R/W [7:0] 0x0 SCL_ORIGHPOS_2 0x0A0C R/W [7:0] 0x0 SCL_ORIGHPOS_3 0x0A0D RW [2:0] 0x0 SCL_ORIGVPOS_E_0 0x0A0E R/W [7:0] 0x0 2’s complement, signed number 27-bit vertical position of the first output pixel of the even frame = (-dest_vpos_e * scalefactor_v) >> 5 SCL_ORIGVPOS_E_1 0x0A0F R/W [7:0] SCL_ORIGVPOS_E_2 0x0A10 R/W [7:0] 0x0 SCL_ORIGVPOS_E_3 0x0A11 R/W [2:0] SCL_THRES_SLOPE 0x0A16 [7:6] 0x0 Reserved R/W [5:0] 0x28 Slope of the contrast amplification function SCL_THRES_OFFSET_L 0x0A17 R/W [7:0] 0x40 Offset of the contrast amplification function [7:0] SCL_THRES_OFFSET_H 0x0A18 [7:2] 0x0 Reserved R/W [1:0] 0x2 Offset of the contrast amplification function [9:8] SCL_CBBYPASS 0x0A19 R/W [7:2] 0x0 Reserved [1] 0x0 0: Normal 1: TCON control of contrast amplification R/W [0] 0x0 0: Contrast Amplification enabled 1: Bypass Contrast Amplification SCL_CON_CAL_SEL 0x0A1A [7:1] Reserved R/W [0] 0x0 0: Context = max of RGB pk-pk 1: Context = sum of RGB pk-pk SCL_TESTCON 0x0A1B [7:2] 6-bit contrast amplification test data R/W [1:0] 0x0 0x0, 0x3: normal 0x1: force input data into the contrast amplification function to bits [7:2] 0x2: force the output context data to be bits [5:2] SCL_LUT1 0x0A1C R/W [7:0] 0xFA Sigmoidal Function LUT Entry 1, 8-bit 2’s complement SCL_LUT2 0x0A1D R/W [7:0] 0xF7 Sigmoidal Function LUT Entry 2, 8-bit 2’s complement SCL_LUT3 0x0A1E R/W [7:0] 0xF7 Sigmoidal Function LUT Entry 3, 8-bit 2’s complement SCL_LUT4 0x0A1F R/W [7:0] 0xFC Sigmoidal Function LUT Entry 4, 8-bit 2’s complement SCL_LUT5 0x0A20 R/W [7:0] 0x2 Sigmoidal Function LUT Entry 5, 8-bit 2’s complement SCL_LUT6 0x0A21 R/W [7:0] 0x0D Sigmoidal Function LUT Entry 6, 8-bit 2’s complement Table 15: LCD Scaler Registers (Sheet 2 of 3) Register Name Addr Mode Bits Default Description |
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