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ADE3700 数据表(PDF) 15 Page - STMicroelectronics

部件名 ADE3700
功能描述  Analog LCD Display Engine for XGA and SXGA Resolutions
PDF  89 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

ADE3700 数据表(HTML) 15 Page - STMicroelectronics

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ADE3700
Global Control
GLBL_SCLK_MD_SD
0x000A
R/W
[7:3]
0x0
SCLK frequency synthesizer MD, range is
[16,31]
R/W
[2:0]
0x0
SCLK frequency synthesizer SDIV, range is
[0,7]
GLBL_SCLK_PE_L
0x000B
R/W
[7:0]
0x0
SCLK frequency synthesizer PE, range is
[0, 32767]
GLBL_SCLK_PE_H
0x000C
R/W
[7:0]
GLBL_TST_CTRL
0x000D
[7:1]
0x0
Reserved
R/W
[0]
0x0
functional test mode enable
GLBL_COMP_PAD_CTRL
0x000E
[7:2]
0x0
Reserved
R/W
[1]
0x0
Compensation pad TQ (test mode)
R/W
[0]
0x1
Compensation pad EN (enable)
GLBL_SCLK_CTRL
0x0010
[7:5]
0x0
Reserved
R/W
[4]
0x0
invert SCLK
[3]
0x0
Reserved
R/W
[2:0]
0x0
SCLK source select
0x0: TESTCLK pin
0x1: SCLK freq synth
0x2: FM freq synth (normal)
0x3: INCLK source
0x4: CLKIN pin
0x5: crystal clock
0x6: 0
0x7: Reserved
GLBL_BPAD_EN
0x0011
R/W
[3:0]
0x0
For each bit n (0 to 3) in the LS nibble,
0: TCON[n] pin is TCON output
1: TCON[n] pin is input for testing
R/W
[4]
0x0
Port B input mode enable (production test
only)
GLBL_IK_SRST
0x0020
R/W
[7]
0x0
Reserved
R/W
[6]
0x0
DFT block reset synchronous to INCLK
R/W
[5]
0x0
ADC block reset synchronous to INCLK
R/W
[4]
0x0
SCALER block reset synchronous to
INCLK
R/W
[3]
0x0
Reserved
R/W
[2]
0x0
Reserved
R/W
[1]
0x0
DMEAS block reset synchronous to INCLK
R/W
[0]
0x0
SMUX block reset synchronous to INCLK
GLBL_SHADOW_EN
0x0021
[7:1]
0x0
Reserved
R/W
[0]
0x0
Shadow registers sync on frame boundary
Table 4: Global Registers (Sheet 3 of 4)
Register Name
Addr.
mode
Bits
Default
Description



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