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ADE3700

Sync Multiplexer (SMUX)

2.7.1

Functional Description

The internal signal selector selects which of the input sources are to be used for the internal hsync,

vsync and enab signals and is controlled by I2C register SMUX_CTRL0.

The signal generator contains a horizontal and a vertical counter that are resynced using a

horizontal and vertical reference signals respectively. The selection of the H/V references and the

resync edge (either rising or falling) are programmed via SMUX_CTRL1[3:0]. The signal generator

requires both references to be defined, or else the counters will not run properly and the generated

signals (other than venab) will be invalid.

The output signal selector can be programmed to output any of the internal syncs, bypassed signals

such as odd and data_valid, or the generated versions of all the signals (hsync, vsync, enab, odd,

valid). Vertical enable (venab) and clamp are always generated.

The following table summarizes programming for typical modes.

Other sources (such as composite sync) are simple variations on these basic configurations.

The programmed timing values of the generated signals (such as clamp) are relative to the

reference signal and edge selected. For example, if the LLK_HSYNC falling edge is selected as the

horizontal reference, then all horizontal programming values are relative to it.

Three signals are generated using programmable set/reset values: clamp and the two components

that make up the input enable signal (horizontal and vertical enables). The henab and venab signals

define the video window that the scaler operates on. The difference between the reset and set

quantities is the number of pixels (h) or lines (v) in the input image. Clean wraparound is supported:

the henab_set can be greater than the henab_rst.

The clamp pulse should be located outside the active video area, i.e. both programmed values

should be in the horizontal blanking region, typically in backporch of the incoming sync.

All set/reset programming values for clamp and henab must be less than the input horizontal total.

Both set/reset programming values for venab must be less than the input vertical total. The updates

for the enable registers can occur in four modes:

1. No Shadowing

2. Simple Shadowing: updates occur when the upper byte of _rst is written

3. Shadowing + Blank Update: updates occur only in the next blanking region after rst_u is written

4. Shadowing + Vblank Update: updates occur in the next vblank region after rst_u is written.

This mode also advances or retards the frame trigger to the scaler to prevent glitches. It takes

one frame to write H and two frames to write the V-position. With large position changes, a

glitch will show up. For small changes (e.g. ±1) no glitch is created.

The written position values are instantly available by read back, independent of shadow mode. The

actual values being used by the hardware at a given time can also be read back using separate I²C

addresses.

Table 10: Sync Multiplexer Programming Table

Mode

Valid Inputs

Output Source for

Hsync

Vsync

Enab

Valid

Odd

Venab

Clamp

Analog

Line Lock

LLK_HSYNC

LLK_VSYNC

LLK

GEN

Analog Ext.

Clock

VGA_HSYNC

LLK_VSYNC

TESTCLK

VGA

LLK

GEN

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