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ADE3700 数据表(PDF) 13 Page - STMicroelectronics |
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ADE3700 数据表(HTML) 13 Page - STMicroelectronics |
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13 / 89 page  13/89 ADE3700 Global Control Table 4: Global Registers (Sheet 1 of 4) Register Name Addr. mode Bits Default Description GLBL_NULL_ADDR 0x0000 Read [7:0] Chip Revision ID GLBL_CLK_SRC_SEL_0 0x0001 [7] 0x0 Reserved R/W [6:4] 0x5 DOTCLK source 0x0: TESTCLK pin 0x1: SCLK freq synth 0x2: FM freq synth (normal) 0x3: INCLK source 0x4: CLKIN pin 0x5: crystal clock 0x6: 0 0x7: Reserved R/W [3:0] 0xA INCLK source 0x0: TESTCLK pin 0x1: nc 0x2: ADC clock red 0x3: ADC clock green 0x4: ADC clock blue 0x5: SCLK freq synth 0x6: nc 0x7: LLK PLL (ADC Input) 0x8: CLKIN pin 0x9: FM freq synth 0xA: crystal clock 0xB: 0 0xC - 0xF: Reserved GLBL_CLK_SRC_SEL_2 0x0002 [7] 0x0 Reserved R/W [6:4] 0x4 LLK CTRL CLK source 0x0: TESTCLK pin 0x1: SCLK freq synth 0x2: LLKPLL control clock (normal) 0x3: CLKIN pin 0x4: crystal clock 0x5: 0 0x6 - 0x7: Reserved [3] Reserved R/W [2:0] 0x4 LLK ZERO CLK source 0x0: TESTCLK pin 0x1: SCLK freq synth 0x2: LLKPLL zero clock (normal) 0x3: CLKIN pin 0x4: crystal clock 0x5: 0 0x6 - 0x7: Reserved |
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