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ADE3700 数据表(PDF) 19 Page - STMicroelectronics

部件名 ADE3700
功能描述  Analog LCD Display Engine for XGA and SXGA Resolutions
PDF  89 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

ADE3700 数据表(HTML) 19 Page - STMicroelectronics

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ADE3700
Line Lock PLL
Table 7: Line Lock PLL Registers (Sheet 1 of 4)
Register Name
Addr
Mode
Bits
Default
Description
LLK_PLL_CLEAR
0x0800
[7:6]
Reserved
R/W
[5]
0x0
master reset
R/W
[4]
0x0
reset the PLL synthetic sync
R/W
[3]
0x0
reset PLL offset
R/W
[2]
0x0
reset PLL accumulator
R/W
[1]
0x0
reset the low pass filter
R/W
[0]
0x0
reset the PLL phase error
LLK_PLL_CTRL
0x0801
R/W
[7]
Reserved
R/W
[6]
0x0
zero clock delay enable
R/W
[5]
0x0
0: normal
1: diagnostic mode -- PLL uses only fine
error
R/W
[4]
0x0
0: normal
1: diagnostic -- coarse error is multiplied by
2
R/W
[3]
0x0
input hsync edge selection
0: rising edge
1: falling edge
R/W
[2]
0x0
sync on green input selection
0: composite sync (HSYNC pin)
1: sync on green (CSYNC pin)
R/W
[1]
0x0
0: normal
1: divide PLL clock by 2
R/W
[0]
0x0
0: normal
1: free-running mode
LLK_PLL_MFACTOR_L
0x0802
R/W
[7:0]
0x0280
number of clocks in a line
LLK_PLL_MFACTOR_H
0x0803
R/W
[7:0]
LLK_PLL_HPERIOD_L
0x0804
R/W
[7:0]
0x0040
pulse width of synthetic hsync
LLK_PLL_HPERIOD_H
0x0805
R/W
[7:0]
LLK_PLL_PHASE_RATE_INIT_0
0x0806
R/W
[7:0]
0x0
initial phase rate
LLK_PLL_PHASE_RATE_INIT_1
0x0807
R/W
[7:0]
fout = fxtal * 227+NDIV / phase_rate
LLK_PLL_PHASE_RATE_INIT_2
0x0808
R/W
[7:0]
LLK_PLL_PHASE_RATE_INIT_3
0x0809
R/W
[7:0]
LLK_PLL_PHASE_RATE_INIT_WR
0x080A
R/W
[7:1]
Reserved
[0]
When written to 1, the pll phase rate is
initialized with the initial phase rate
register. Self clearing.



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