ADE3700 datasheet(14/89 Pages) STMICROELECTRONICS

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Global Control

ADE3700

14/89

GLBL_CLK_INV

0x0003

[7:5]

0x0

Reserved

R/W

[4]

0x0

Invert LLPLL control clock

R/W

[3]

0x0

Invert LLPLL zero clock

R/W

[2]

0x0

Invert ADC sample clock

R/W

[1]

0x0

Invert DOT clock

R/W

[0]

0x0

Invert input clock

GLBL_CLK_ENABLE_0

0x0004

[7:1]

0x0

Reserved

R/W

[0]

0x1

Clock enable async override

GLBL_ANA_PWR

0x0005

[7:5]

0x0

Reserved

R/W

[4]

0x1

Blue ADC power down

R/W

[3]

0x1

Green ADC power down

R/W

[2]

0x1

Red ADC power down

[1:0]

0x0

Reserved

GLBL_XK_SRST

0x0006

[7:3]

0x0

Reserved

R/W

[2]

0x0

SMEAS block reset, synchronous to XCLK

R/W

[1]

0x0

SRT block reset, synchronous to XCLK

R/W

[0]

0x0

Frame Sync block reset, synchronous to

XCLK

GLBL_I2C_CTRL

0x0007

[7:3]

0x0

Reserved

R/W

[2]

0x0

Disable I2C auto increment

R/W

[1]

0x0

SDA PMOS enable

R/W

[0]

0x0

bypass I2C filter

GLBL_XTAL_CTRL

0x0008

[7:1]

0x0

Reserved

R/W

[0]

0x1

crystal oscillator enable

GLBL_SCLK_SYNTH_CTRL

0x0009

[7:5]

0x0

Reserved

R/W

[4:3]

0x0

XTAL frequency multiplier NDIV

0x0: fXCLK = 54MHz

0x1: fXCLK = 27MHz (normal)

0x2: fXCLK = 13.5MHz

0x3: Reserved

R/W

[2]

0x0

SCLK frequency synthesizer EXT_PLL

(normal operation = 0)

R/W

[1]

0x0

SCLK frequency synthesizer PLL_SEL

(normal operation = 1)

R/W

[0]

0x1

SCLK freq synth control disable (normal

operation = 0)

Table 4: Global Registers (Sheet 2 of 4)

Addr.

mode

Bits

Default

Description

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ADE3700 数据表(PDF) 14 Page - STMicroelectronics

ADE3700 数据表(HTML) 14 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89

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