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ADE3700 数据表(PDF) 25 Page - STMicroelectronics

部件名 ADE3700
功能描述  Analog LCD Display Engine for XGA and SXGA Resolutions
PDF  89 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

ADE3700 数据表(HTML) 25 Page - STMicroelectronics

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ADE3700
Sync Measurement
2.6
Sync Measurement
The Input Sync Measurement (SMEAS) block continuously detects activity from all video sources.
The module can measure the characteristics of the sync signals on any input port. The sync
measurement module reports the results of the measurements to the system microcontroller.
This portion of the sync measurement is fully synchronous on the crystal clock (XCLK). Another
block, the Sync Retiming Block (SRT), handles the asynchronous signal transfer of the incoming
sync signals.
Input Sync Functions:
q
Activity Detection
q
Sync Management
q
Measurement
Table 9: Sync Measurement (Sheet 1 of 8)
Register Name
Addr
Mode
Bits
Default
Description
SMEAS_ACT_CTRL
0x0100
[7:4]
0x0
Reserved
R/W
[3]
0x0
Enable activity detection in free-running
mode.
R/W
[2]
0x0
Freeze results in free-running mode. No
meaning in one shot mode.
0: Do not freeze the results. New result will
be available on the next and subsequent
toggle of the polling bit.
1: Freeze the current results. The polling bit
will still toggle and the block continues to
free-run; however, results will not be
updated.
R/W
[1]
0x0
activity detection start.
In one-shot mode it triggers the start of a
measurement and is reset to zero when the
measurement is complete.
R/W
[0]
0x0
activity detection mode control
0: free-running
1: one shot
SMEAS_ACT_H_SMPTM_L
0x0101
R/W
[7:0]
0x0
Sample time value for clock or hsync
activity. In units of XCLK_period*256
SMEAS_ACT_H_SMPTM_H
0x0102
R/W
[7:0]
0x0
SMEAS_ACT_V_SMPTM_L
0x0103
R/W
[7:0]
0x0
Sample time value for vsync activity in units
of XCLK_period*256. jj
Note: this number MUST be larger than
hsync sample time.
SMEAS_ACT_V_SMPTM_H
0x0104
R/W
[7:0]
0x0
SMEAS_ACT_H_MINEDGE
0x0105
R/W
[7:0]
0x0
Minimum edge count value for clk or hsync
activity.
SMEAS_ACT_V_MINEDGE
0x0106
R/W
[7:0]
0x0
Minimum edge count value for vsync
activity.
SMEAS_H_TMOT_L
0x0107
R/W
[7:0]
0x4000
timeout counter value for clk or horizontal
measurement in XCLKs
SMEAS_H_TMOT_H
0x0108
R/W
[7:0]



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