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ADE3700 数据表(PDF) 37 Page - STMicroelectronics

部件名 ADE3700
功能描述  Analog LCD Display Engine for XGA and SXGA Resolutions
PDF  89 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

ADE3700 数据表(HTML) 37 Page - STMicroelectronics

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ADE3700
Data Multiplexer
2.8
Data Multiplexer
The Data Multiplexer provides the following functions:
q
Debug modes (e.g. bit order swap, color swap)
HSYNC_PHASE
0x0210
R/W
[7:0]
0x00
number of horizontal pixels/INCLKS that the
generated hsync edge is from the reference
edge. 2’s complement
[-128,127]
VSYNC_PHASE
0x0211
R/W
[7:0]
0x00
number of vertical lines that the generated vsync
edge is from the reference edge. 2’s complement
[-128,127]
HENAB_SET_HW_L
0x0212
R
[7:0]
Actual value used by hardware post shadowing.
HENAB _SET_HW _U
0x0213
R
[3:0]
Actual value used by hardware post shadowing.
HENAB _RST_HW _L
0x0214
R
[7:0]
Actual value used by hardware post shadowing.
HENAB _RST_HW _U
0x0215
R
[3:0]
Actual value used by hardware post shadowing.
VENAB_SET_HW _L
0x0216
R
[7:0]
Actual value used by hardware post shadowing.
VENAB _SET_HW _U
0x0217
R
[3:0]
Actual value used by hardware post shadowing.
VENAB _RST_HW _L
0x0218
R
[7:0]
Actual value used by hardware post shadowing.
VENAB _RST_HW _U
0x0219
R
[3:0]
Actual value used by hardware post shadowing.
Table 12: Data Mux Registers
Register Name
Addr.
Mode
Bits
Default
Description
DMUX_CHANSEL
0x0280
[7]
0x0
Reserved
R/W
[6]
0x0
0: Normal
1: MSB/LSB byte flip
R/W
[5:3]
0x0
If enabled by [2]
0x0: Reserved
0x1: R & G bytes are swapped
0x2: B & G bytes are swapped
0x3: R => G, G => B, B => R
0x4: R & B bytes are swapped
0x5: R => B, G => R, B => G
0x0, 0x6-0x7: Reserved
R/W
[2]
0x0
0: normal
1: enable color swap
R/W
[1:0]
0x0
video source select
0x0: ADC data
0x1: nc
0x2: nc
0x3: for test only
Table 11: Sync Multiplexer Registers (Sheet 4 of 4)
Register Name
Addr
Mode
Bits
Default
Description



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