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ADE3700 数据表(PDF) 23 Page - STMicroelectronics |
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ADE3700 数据表(HTML) 23 Page - STMicroelectronics |
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23 / 89 page  23/89 ADE3700 Sync Retiming (SRT) 2.5 Sync Retiming (SRT) The Sync Retiming (SRT) block retimes incoming synchronization signals (H Sync, V Sync, etc) into the XCLK and INCLK domains. For the XCLK domain, the SRT has the following functions: q Retimes all sync signals going to SMEAS into the XCLK domain. q Extracts the vertical sync signal from composite sync signals (AHSYNC and ACSYNC pins) q Divides clocks by 1024 for activity detection purposes. q Generates a delay-filtered version of vertical sync from a mux-selectable vertical sync source. q Generates a coast signal in the XCLK domain for the LLPLL. Table 8: Sync Retiming Registers (Sheet 1 of 2) Register Name Addr Mode Bits Default Description SRTXK_CSYNC_INV 0x01E0 [7:3] 0x0 Reserved R/W [2] 0x0 invert filtered vert sync signal R/W [1] 0x0 invert composite sync signal R/W [0] 0x0 invert SOG signal SRTXK_SOG_THR_L 0x01E1 R/W [7:0] 0x080 SOG vert sync extractor threshold [7:0] SRTXK_SOG_THR_H 0x01E2 R/W [7:4] Reserved [3:0] SOG vert sync extractor threshold [11:8] SRTXK_CSYNC_THR_L 0x01E3 R/W [7:0] 0x080 composite sync vertical sync extractor threshold [7:0] SRTXK_CSYNC_THR_H 0x01E4 R/W [7:4] Reserved [3:0] composite sync vertical sync extractor threshold [11:8] SRTXK_VSYNC_SEL 0x01E5 R/W [7:3] Reserved [2:0] 0x0 filtered vert sync source select 0x0: avsync pin 0x1: vsync from composite ahsync pin 0x2: vsync from composite acsync pin 0x3: Reserved 0x4 - 0x7: Reserved SRTXK_VSYNC_THR_L 0x01E6 R/W [7:0] 0x080 filtered vert sync delay [7:0] SRTXK_VSYNC_THR_H 0x01E7 R/W [7:4] Reserved R/W [3:0] filtered vert sync delay [11:8] |
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